Add to SP (register) adds an optionally-shifted register value to the SP value, and writes the result to the destination register.
If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | S | 1 | 1 | 0 | 1 | Rd | imm5 | stype | 0 | Rm | ||||||||||||||
cond |
constant d = UInt(Rd); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm5);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | DM | 1 | 1 | 0 | 1 | Rdm |
constant d = UInt(DM:Rdm); constant m = UInt(DM:Rdm); constant setflags = FALSE; constant (shift_t, shift_n) = (SRType_LSL, 0); if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | != 1101 | 1 | 0 | 1 | |||
Rm |
if Rm == '1101' then SEE "encoding T1"; constant d = 13; constant m = UInt(Rm); constant setflags = FALSE; constant (shift_t, shift_n) = (SRType_LSL, 0);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | S | 1 | 1 | 0 | 1 | (0) | imm3 | Rd | imm2 | stype | Rm |
ADD{<c>}.W {<Rd>,} SP, <Rm> // (<Rd>, <Rm> can be represented in T1 or T2)
if Rd == '1111' && S == '1' then SEE "CMN (register)"; constant d = UInt(Rd); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); // Armv8-A removes UNPREDICTABLE for R13 if (d == 15 && !setflags) || m == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
SP, |
Is the stack pointer. |
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
|
if ConditionPassed() then EncodingSpecificOperations(); constant shifted = Shift(R[m], shift_t, shift_n, PSTATE.C); constant (result, nzcv) = AddWithCarry(R[13], shifted, '0'); if d == 15 then if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.