Copy a general-purpose register to a vector element copies a byte, halfword, or word from a general-purpose register into an Advanced SIMD scalar.
On a Floating-point-only system, this instruction transfers one word to the upper or lower half of a double-precision floating-point register from a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.
For more information about scalars see Advanced SIMD scalars.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 0 | opc1 | 0 | Vd | Rt | 1 | 0 | 1 | 1 | D | opc2 | 1 | (0) | (0) | (0) | (0) | |||||||||||
cond |
boolean advsimd; integer index; case opc1:opc2 of when '1xxx' advsimd = TRUE; index = UInt(opc1<0>:opc2); when '0xx1' advsimd = TRUE; index = UInt(opc1<0>:opc2<1>); when '0x00' advsimd = FALSE; index = UInt(opc1<0>); when '0x10' UNDEFINED; constant integer esize = if opc1<1> == '1' then 8 else 32 >> UInt(opc2<0>); constant d = UInt(D:Vd); constant t = UInt(Rt); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | opc1 | 0 | Vd | Rt | 1 | 0 | 1 | 1 | D | opc2 | 1 | (0) | (0) | (0) | (0) |
boolean advsimd; integer index; case opc1:opc2 of when '1xxx' advsimd = TRUE; index = UInt(opc1<0>:opc2); when '0xx1' advsimd = TRUE; index = UInt(opc1<0>:opc2<1>); when '0x00' advsimd = FALSE; index = UInt(opc1<0>); when '0x10' UNDEFINED; constant integer esize = if opc1<1> == '1' then 8 else 32 >> UInt(opc2<0>); constant d = UInt(D:Vd); constant t = UInt(Rt); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Dd[x]> |
The scalar. The register <Dd> is encoded in D:Vd. For details of how [x] is encoded, see the description of <size>. |
<Rt> |
The source general-purpose register. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); Elem[D[d],index,esize] = R[t]<esize-1:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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