Add (extended register) adds a Capability register value field and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination Capability register value field. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. If the result is not representable the destination Capability register tag is cleared. If the source capability is sealed, the Capability Tag written to the destination Capability register is cleared.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Rm | option | imm3 | Cn | Cd |
integer d = UInt(Cd); integer n = UInt(Cn); integer m = UInt(Rm); ExtendType extend_type = DecodeRegExtend(option); integer shift = UInt(imm3); if shift > 4 then UNDEFINED;
<Cd|CSP> |
Is the capability name of the destination register or stack pointer, encoded in the "Cd" field. |
<Cn|CSP> |
Is the capability name of the source register or stack pointer, encoded in the "Cn" field. |
<Xm> |
Is the 64-bit name of the source general-purpose register, encoded in the "Rm" field. |
<extend> |
Is the index extend and shift specifier,
encoded in
option:
|
<amount> |
Is the optional unsigned immediate operand, in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. |
CheckCapabilitiesEnabled(); Capability operand1 = if n == 31 then CSP[] else C[n]; bits(64) operand2 = ExtendReg(m, extend_type, shift); Capability result = CapAdd(operand1, operand2); if CapIsSealed(operand1) then result = CapWithTagClear(result); if d == 31 then CSP[] = result; else C[d] = result;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.