ADD (extended register)

Add (extended register) adds a Capability register value field and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination Capability register value field. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. If the result is not representable the destination Capability register tag is cleared. If the source capability is sealed, the Capability Tag written to the destination Capability register is cleared.

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11000010101Rmoptionimm3CnCd

ADD <Cd|CSP>, <Cn|CSP>, <Xm>{, <extend> #<amount>}

integer d = UInt(Cd); integer n = UInt(Cn); integer m = UInt(Rm); ExtendType extend_type = DecodeRegExtend(option); integer shift = UInt(imm3); if shift > 4 then UNDEFINED;

Assembler Symbols

<Cd|CSP>

Is the capability name of the destination register or stack pointer, encoded in the "Cd" field.

<Cn|CSP>

Is the capability name of the source register or stack pointer, encoded in the "Cn" field.

<Xm>

Is the 64-bit name of the source general-purpose register, encoded in the "Rm" field.

<extend> Is the index extend and shift specifier, encoded in option:
option <extend>
000 UXTB
001 UXTH
010 UXTW
011 UXTX
100 SXTB
101 SXTH
110 SXTW
111 SXTX
<amount>

Is the optional unsigned immediate operand, in the range 0 to 4, defaulting to 0, encoded in the "imm3" field.

Operation

CheckCapabilitiesEnabled(); Capability operand1 = if n == 31 then CSP[] else C[n]; bits(64) operand2 = ExtendReg(m, extend_type, shift); Capability result = CapAdd(operand1, operand2); if CapIsSealed(operand1) then result = CapWithTagClear(result); if d == 31 then CSP[] = result; else C[d] = result;


Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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