STR (register, SIMD&FP)

Store SIMD&FP register (register offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
size111100x01RmoptionS10RnRt
opc

8-fsreg,STR-8-fsreg (size == 00 && opc == 00 && option != 011)

STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}] // (PSTATE.C64 == '0')

STR <Bt>, [<Cn|CSP>, (<Wm>|<Xm>), <extend> {<amount>}] // (PSTATE.C64 == '1')

8-fsreg,STR-8-fsreg (size == 00 && opc == 00 && option == 011)

STR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}] // (PSTATE.C64 == '0')

STR <Bt>, [<Cn|CSP>, <Xm>{, LSL <amount>}] // (PSTATE.C64 == '1')

16-fsreg,STR-16-fsreg (size == 01 && opc == 00)

STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')

STR <Ht>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')

32-fsreg,STR-32-fsreg (size == 10 && opc == 00)

STR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')

STR <St>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')

64-fsreg,STR-64-fsreg (size == 11 && opc == 00)

STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')

STR <Dt>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')

128-fsreg,STR-128-fsreg (size == 00 && opc == 10)

STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')

STR <Qt>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then scale else 0;

Assembler Symbols

<Bt>

Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>

Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Ht>

Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>

Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>

Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

<Wm>

When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>

When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

<extend> For the 8-bit variant: is the index extend specifier, encoded in option:
option <extend>
010 UXTW
110 SXTW
111 SXTX
For the 128-bit, 16-bit, 32-bit and 64-bit variant: is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted. encoded in option:
option <extend>
010 UXTW
011 LSL
110 SXTW
111 SXTX
<amount>

For the 8-bit variant: is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present.

For the 16-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:
S <amount>
0 #0
1 #1
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:
S <amount>
0 #0
1 #2
For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:
S <amount>
0 #0
1 #3
For the 128-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:
S <amount>
0 #0
1 #4

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm); AccType acctype = AccType_VEC; MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; integer datasize = 8 << scale;

Operation

bits(64) offset = ExtendReg(m, extend_type, shift); CheckFPAdvSIMDEnabled64(); bits(64) address; bits(datasize) data; VirtualAddress base; base = BaseReg[n]; address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, datasize DIV 8, CAP_PERM_STORE, acctype); data = V[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD VACheckAddress(base, address, datasize DIV 8, CAP_PERM_LOAD, acctype); data = Mem[address, datasize DIV 8, acctype]; V[t] = data; if wback then base = VAAdd(base,offset); BaseReg[n] = base;


Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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