morello_add_extended<extend>
Original text: Is the index extend and shift specifier, encoded in "option", where 000->UXTB, 001->UXTH, 010->UXTW, 011->UXTX, 100->SXTB, 101->SXTH, 110->SXTW and 111->SXTX.
Where:
<extend> |
Is the index extend and shift specifier,
encoded in
option :
option |
<extend> |
000 |
UXTB |
001 |
UXTH |
010 |
UXTW |
011 |
UXTX |
100 |
SXTB |
101 |
SXTH |
110 |
SXTW |
111 |
SXTX |
|
Morello add/subtract capability<amount>
Original text: Is the index shift amount, encoded in "sh", where 0->#0 and 1->#12.
Where:
<amount> |
Is the index shift amount,
encoded in
sh :
|
Morello load/store register via alternate base<amount>
Original text: Is the index shift amount, encoded in "S", where 0->[absent] and 1->#1.
Where:
<amount> |
Is the index shift amount,
encoded in
S :
S |
<amount> |
0 |
[absent] |
1 |
#1 |
|
Morello load/store register via alternate base<amount>
Original text: Is the index shift amount, encoded in "S", where 0->[absent] and 1->#2.
Where:
<amount> |
Is the index shift amount,
encoded in
S :
S |
<amount> |
0 |
[absent] |
1 |
#2 |
|
Morello load/store register via alternate base<amount>
Original text: Is the index shift amount, encoded in "S", where 0->[absent] and 1->#3.
Where:
<amount> |
Is the index shift amount,
encoded in
S :
S |
<amount> |
0 |
[absent] |
1 |
#3 |
|
Morello load/store register via alternate base<extend>
Original text: Is the index extend and shift specifier, encoded in "sign:sz", where 00->UXTW, 01->LSL, 10->SXTW and 11->SXTX.
Where:
<extend> |
Is the index extend and shift specifier,
encoded in
sign:sz :
sign |
sz |
<extend> |
0 |
0 |
UXTW |
0 |
1 |
LSL |
1 |
0 |
SXTW |
1 |
1 |
SXTX |
|
Morello load/store register via alternate base<R>
Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.
Where:
<R> |
Is a width specifier,
encoded in
sz :
|
Morello load/store capability via alternate base<amount>
Original text: Is the index shift amount, encoded in "S", where 0->[absent] and 1->#4.
Where:
<amount> |
Is the index shift amount,
encoded in
S :
S |
<amount> |
0 |
[absent] |
1 |
#4 |
|
Morello load/store capability via alternate base<R>
Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.
Where:
<R> |
Is a width specifier,
encoded in
sz :
|
Morello load/store capability via alternate base<extend>
Original text: Is the index extend and shift specifier, encoded in "sign:sz", where 00->UXTW, 01->LSL, 10->SXTW and 11->SXTX.
Where:
<extend> |
Is the index extend and shift specifier,
encoded in
sign:sz :
sign |
sz |
<extend> |
0 |
0 |
UXTW |
0 |
1 |
LSL |
1 |
0 |
SXTW |
1 |
1 |
SXTX |
|
morello_clear_perm_imm<perm>
Original text: Is the perm specifier, encoded in the "perm" field, where 000->#0, 001->X, 010->W, 011->WX, 100->R, 101->RX, 110->RW and 111->RWX.
Where:
<perm> |
Is the perm specifier,
encoded in
perm :
perm |
<perm> |
000 |
#0 |
001 |
X |
010 |
W |
011 |
WX |
100 |
R |
101 |
RX |
110 |
RW |
111 |
RWX |
|
morello_condsel<cond>
Original text: Is one of the standard conditions, encoded in "cond", where 0000->EQ, 0001->NE, 0010->CS, 0011->CC, 0100->MI, 0101->PL, 0110->VS, 0111->VC, 1000->HI, 1001->LS, 1010->GE, 1011->LT, 1100->GT, 1101->LE, 1110->AL and 1111->NV.
Where:
<cond> |
Is one of the standard conditions,
encoded in
cond :
cond |
<cond> |
0000 |
EQ |
0001 |
NE |
0010 |
CS |
0011 |
CC |
0100 |
MI |
0101 |
PL |
0110 |
VS |
0111 |
VC |
1000 |
HI |
1001 |
LS |
1010 |
GE |
1011 |
LT |
1100 |
GT |
1101 |
LE |
1110 |
AL |
1111 |
NV |
|
Morello load/store register<R>
Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.
Where:
<R> |
Is a width specifier,
encoded in
sz :
|
Morello load/store register<extend>
Original text: Is the index extend and shift specifier, encoded in "sign:sz", where 00->UXTW, 01->LSL, 10->SXTW and 11->SXTX.
Where:
<extend> |
Is the index extend and shift specifier,
encoded in
sign:sz :
sign |
sz |
<extend> |
0 |
0 |
UXTW |
0 |
1 |
LSL |
1 |
0 |
SXTW |
1 |
1 |
SXTX |
|
Morello load/store register<amount>
Original text: Is the index shift amount, encoded in "S", where 0->[absent] and 1->#4.
Where:
<amount> |
Is the index shift amount,
encoded in
S :
S |
<amount> |
0 |
[absent] |
1 |
#4 |
|
Morello get/set system register<op0>
Original text: Is the op0 specifier, encoded in the "o0" field, where 0->2 and 1->3.
Where:
<op0> |
Is the op0 specifier,
encoded in
o0 :
|
Morello immediate seal<form>
Original text: Is the form specifier, encoded in the "form" field, where 00->RESERVED, 01->rb, 10->lpb and 11->lb.
Where:
<form> |
Is the form specifier,
encoded in
form :
form |
<form> |
00 |
RESERVED |
01 |
rb |
10 |
lpb |
11 |
lb |
|
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2
; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2015 Arm Limited or its affiliates. All rights reserved.
This document is Non-Confidential.