Load capability (register) via alternate base determines the base register to be used, derives an address from the base register and an offset register, loads a capability from memory, and writes it to the destination Capability register. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. The offset register can optionally be shifted and extended. For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | Rm | sign | 1 | sz | S | 1 | 1 | Rn | Ct | ||||||||||||
L |
LDR <Ct>, [<Cn|CSP>, <R><m>{, <extend> <amount>}] // (PSTATE.C64 == '0')
LDR <Ct>, [<Xn|SP>, <R><m>{, <extend> <amount>}] // (PSTATE.C64 == '1')
integer t = UInt(Ct); integer n = UInt(Rn); integer m = UInt(Rm); integer scale = LOG2_CAPABILITY_DBYTES; ExtendType extend_type = DecodeRegExtend(sign:'1':sz); integer shift = if S == '1' then scale else 0;
<Ct> |
Is the capability name of the transfer register, encoded in the "Ct" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
<R> |
Is a width specifier,
encoded in
sz:
|
<m> |
Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field. |
<extend> |
Is the index extend and shift specifier,
encoded in
sign:sz:
|
<amount> |
Is the index shift amount,
encoded in
S:
|
CheckCapabilitiesEnabled(); bits(64) offset = ExtendReg(m, extend_type, shift); VirtualAddress base = AltBaseReg[n]; Capability data; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, AccType_NORMAL); data = MemC[addr, AccType_NORMAL]; data = CapSquashPostLoadCap(data, base); C[t] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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