Load SIMD&FP Register (register offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
size | 1 | 1 | 1 | 1 | 0 | 0 | x | 1 | 1 | Rm | option | S | 1 | 0 | Rn | Rt | |||||||||||||||
opc |
LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}] // (PSTATE.C64 == '0')
LDR <Bt>, [<Cn|CSP>, (<Wm>|<Xm>), <extend> {<amount>}] // (PSTATE.C64 == '1')
LDR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}] // (PSTATE.C64 == '0')
LDR <Bt>, [<Cn|CSP>, <Xm>{, LSL <amount>}] // (PSTATE.C64 == '1')
LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')
LDR <Ht>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')
LDR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')
LDR <St>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')
LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')
LDR <Dt>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')
LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '0')
LDR <Qt>, [<Cn|CSP>, (<Wm>|<Xm>){, <extend> {<amount>}}] // (PSTATE.C64 == '1')
boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then scale else 0;
<Bt> |
Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Dt> |
Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Ht> |
Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Qt> |
Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<St> |
Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Cn|CSP> |
Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field. |
<Wm> |
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field. |
<Xm> |
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field. |
<amount> |
For the 8-bit variant: is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present. | ||||||
For the 16-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
| |||||||
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
| |||||||
For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
| |||||||
For the 128-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
|
integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm); AccType acctype = AccType_VEC; MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; integer datasize = 8 << scale;
bits(64) offset = ExtendReg(m, extend_type, shift); CheckFPAdvSIMDEnabled64(); bits(64) address; bits(datasize) data; VirtualAddress base; base = BaseReg[n]; address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, datasize DIV 8, CAP_PERM_STORE, acctype); data = V[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD VACheckAddress(base, address, datasize DIV 8, CAP_PERM_LOAD, acctype); data = Mem[address, datasize DIV 8, acctype]; V[t] = data; if wback then base = VAAdd(base,offset); BaseReg[n] = base;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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