CCTLR_EL3, Capability Control Register (EL3)

The CCTLR_EL3 characteristics are:

Purpose

Provides control of capability-related functionality at EL3.

Configuration

This register is present only when Morello is implemented and HaveEL(EL3). Otherwise, direct accesses to CCTLR_EL3 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CCTLR_EL3 is a 64-bit register.

Field descriptions

The CCTLR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0SBLPERMVCTC64EADRDPBPCCBODDCBORES0TGEN0
313029282726252423222120191817161514131211109876543210

Bits [63:8]

Reserved, RES0.

SBL, bit [7]

Controls whether branch-and-link instructions at EL3 seal the capability generated in C30.

Controls whether the following instructions at EL3 require a target capability with ObjectType set to 1:

BLRR, BLRS (capability), BRR, BRS (capability), RETR, RETS (capability).

SBLMeaning
0b0

Branch-and-link instructions which generate a capability in C30 do not seal the capability.

The specified instructions do not require a target capability with ObjectType set to 1.

0b1

Branch-and-link instructions which generate a capability in C30 seal the generated capability with ObjectType set to 1.

The specified instructions require a target capability with ObjectType set to 1.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

PERMVCT, bit [6]

Permits access to CNTVCT_EL0 without PCC System permission at EL3

PERMVCTMeaning
0b0

Access to CNTVCT_EL0 at EL3 requires PCC System permission

0b1

This field has no effect

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

C64E, bit [5]

Capability mode on exception entry to EL3

C64EMeaning
0b0

On exception entry PSTATE.C64 is set to 0.

0b1

On exception entry PSTATE.C64 is set to 1.

In a system where the PE resets into EL3, this field resets to 0.

ADRDPB, bit [4]

ADRDP instruction base register selection at EL3

ADRDPBMeaning
0b0

ADRDP uses DDC as a base register

0b1

ADRDP uses C28 as a base register

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

PCCBO, bit [3]

PCC base offset enable for A64 instructions writing PC or generating a PC derived 64-bit value at EL3

PCCBOMeaning
0b0

Accesses do not add PCC base to the address written to PC, and do not subtract PCC base from the address read from PCC.

0b1

Accesses add PCC base to the address written to PC, and subtract PCC base from the address read from PCC.

Note: this affects the following instructions:

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

DDCBO, bit [2]

DDC base offset enable for accesses using a 64-bit base register at EL3

DDCBOMeaning
0b0

Accesses do not add or subtract DDC base from the accessed address.

0b1

Accesses add or subtract DDC base from the accessed address, depending on the instruction.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

Bit [1]

Reserved, RES0.

TGEN0, bit [0]

Tag generation bit for TTBR0_EL3 based accesses

TGEN0Meaning
0b0

Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b11.

0b1

Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b10.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

Accessing the CCTLR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, CCTLR_EL3

op0op1CRnCRmop2
0b110b1100b00010b00100b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL3;

MSR CCTLR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00100b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL3 = X[t];




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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