The PMVIDSR characteristics are:
Contains the sampled VMID value that is captured on reading PMPCSR[31:0].
PMVIDSR is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
This register is present only when ARMv8.2-PCSample is implemented and HaveEL(EL2). Otherwise, direct accesses to PMVIDSR are RES0.
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMVIDSR is a 32-bit register.
The PMVIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | VMID[15:8] | VMID |
Reserved, RES0.
Extension to VMID[7:0]. See VMID[7:0] for more details.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
VMID sample. The VMID associated with the most recent PMPCSR sample. When the most recent PMPCSR sample was generated:
Because the value written to PMVIDR is an indirect read of the VMID value, it is CONSTRAINED UNPREDICTABLE whether PMVIDSR is set to the original or new value if PMPCSR samples:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance |
---|---|---|
PMU | 0x20C | PMVIDSR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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