The ID_ISAR6_EL1 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1 and ID_ISAR5_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register ID_ISAR6_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR6[31:0] .
This register is present only from Armv8.2. Otherwise, direct accesses to ID_ISAR6_EL1 are RES0. In an implementation that supports only AArch64 state, this register is UNKNOWN.
ID_ISAR6_EL1 is a 64-bit register.
The ID_ISAR6_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | I8MM | BF16 | SPECRES | SB | FHM | DP | JSCVT | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates support for Advanced SIMD and floating-point Int8 matrix multiplication instructions in AArch32 state. Defined values of this field are:
I8MM | Meaning |
---|---|
0b0000 |
Int8 matrix multiplication instructions are not implemented. |
0b0001 |
VSMMLA, VSUDOT, VUMMLA, VUSMMLA, and VUSDOT instructions are implemented. |
All other values are reserved.
ARMv8.2-AA32I8MM implements the functionality identified by 0b0001.
Reserved, RES0.
Indicates support for Advanced SIMD and floating-point BFloat16 instructions in AArch32 state. Defined values are:
BF16 | Meaning |
---|---|
0b0000 |
BFloat16 instructions are not implemented. |
0b0001 |
VCVT, VCVTB, VCVTT, VDOT, VFMAL, and VMMLA instructions with BF16 operand or result types are implemented. |
All other values are reserved.
ARMv8.2-AA32BF16 implements the functionality identified by 0b0001.
Reserved, RES0.
Indicates supporte for Speculation invalidation instruction in AArch32 state. Defined values are:
SPECRES | Meaning |
---|---|
0b0000 |
CFPRCTX, DVPRCTX, and CPPRCTX instructions are not implemented. |
0b0001 |
CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented. |
All other values are reserved.
From Armv8.5, the only permitted value is 0b0001.
Indicates support for SB instruction in AArch32 state. Defined values are:
SB | Meaning |
---|---|
0b0000 |
SB instruction is not implemented. |
0b0001 |
SB instruction is implemented. |
All other values are reserved.
From Armv8.5, the only permitted value is 0b0001.
Indicates support for Advanced SIMD and floating-point VFMAL and VFMSL instructions in AArch32 state. Defined values are:
FHM | Meaning |
---|---|
0b0000 |
VFMAL and VMFSL instructions are not implemented. |
0b0001 |
VFMAL and VMFSL instructions are implemented. |
ARMv8.2-FHM implements the functionality identified by the value 0b0001.
In Armv8.0 and Armv8.1, the only permitted value is 0b0000.
In Armv8.2, the permitted values are 0b0000 and 0b0001.
Indicates the support for dot product instructions in AArch32 state. Defined values are:
DP | Meaning |
---|---|
0b0000 |
No dot product instructions are implemented. |
0b0001 |
VUDOT and VSDOT instructions are implemented. |
All other values are reserved.
ARMv8.2-DotProd implements the functionality identified by the value 0b0001.
In Armv8.0 and Armv8.1, the only permitted value is 0b0000.
In Armv8.2, the permitted values are 0b0000 and 0b0001.
Indicates support for the Javascript conversion instruction in AArch32 state. Defined values are:
JSCVT | Meaning |
---|---|
0b0000 |
The VJCVT instruction is not implemented. |
0b0001 |
The VJCVT instruction is implemented. |
All other values are reserved.
ARMv8.3-JSConv implements the functionality identified by 0b0001.
In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.
From Armv8.3, the only permitted value is 0b0001.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0010 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6_EL1) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_ISAR6_EL1; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); else return ID_ISAR6_EL1; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return ID_ISAR6_EL1;
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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