The CNTSR characteristics are:
Provides counter frequency status information.
The power domain of CNTSR is IMPLEMENTATION DEFINED. Some or all RW fields of this register have defined reset values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTSR is a 32-bit register.
The CNTSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FCACK | RES0 | DBGH | RES0 |
Frequency change acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table'.
This field resets to 0.
Reserved, RES0.
Indicates whether the counter is halted because the Halt-on-debug signal is asserted:
DBGH | Meaning |
---|---|
0b0 |
Counter is not halted. |
0b1 |
Counter is halted. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTControlBase | 0x004 | CNTSR |
Accesses on this interface are RO.
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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