The TLBI IPAS2E1IS characteristics are:
If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 2 only translation table entry, from any level of the translation table walk.
One of the following applies:
The entry would be used with the current VMID.
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
For more information about the architectural requirements for this System instruction, see 'Invalidation of TLB entries from stage 2 translations'.
TLBI IPAS2E1IS is a 64-bit System instruction.
The TLBI IPAS2E1IS input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | IPA[51:48] | IPA[47:12] | |||||||||||||||||||||||||||||
IPA[47:12] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Extension to IPA[47:12]. See IPA[47:12] for more details.
Reserved, RES0.
Bits[47:12] of the intermediate physical address to match. For implementations with fewer than 48 bits, the upper bits of this field are RES0.
When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, IPA[51:48] form the upper part of the address value. Otherwise, IPA[51:48] are RES0.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); else TLBI_IPAS2E1IS(R[t]); elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif !EL2Enabled() then //no operation else TLBI_IPAS2E1IS(R[t]);
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.