The TPIDR_EL2 characteristics are:
Provides a location where software executing at EL2 can store thread identifying information, for OS management purposes.
The PE makes no use of this register.
AArch64 System register TPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HTPIDR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
TPIDR_EL2 is a 129-bit register.
The TPIDR_EL2 bit assignments are:
Thread ID. Thread identifying information stored by software running at this Exception level
This field resets to an architecturally UNKNOWN value.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Thread ID | |||||||||||||||||||||||||||||||
Thread ID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Thread ID. Thread identifying information stored by software running at this Exception level.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && IsInRestricted() && !Halted() then return RTPIDR_EL0<63:0>; else return TPIDR_EL2<63:0>; elsif PSTATE.EL == EL3 then return TPIDR_EL2<63:0>;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && IsInRestricted() && !Halted() then RTPIDR_EL0 = ZeroExtend(X[t]); else TPIDR_EL2 = ZeroExtend(X[t]); elsif PSTATE.EL == EL3 then TPIDR_EL2 = ZeroExtend(X[t]);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); elsif IsFeatureImplemented("Morello") && IsInRestricted() && !Halted() then return RTPIDR_EL0; else return TPIDR_EL2; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return TPIDR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); elsif IsFeatureImplemented("Morello") && IsInRestricted() && !Halted() then RTPIDR_EL0 = C[t]; else TPIDR_EL2 = C[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else TPIDR_EL2 = C[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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