The MDCR_EL3 characteristics are:
Provides EL3 configuration options for self-hosted debug and the Performance Monitors Extension.
AArch64 System register MDCR_EL3 bits [31:0] can be mapped to AArch32 System register SDCR[31:0] , but this is not architecturally mandated.
This register is present only when HaveEL(EL3). Otherwise, direct accesses to MDCR_EL3 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
MDCR_EL3 is a 64-bit register.
The MDCR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | EPMAD | EDAD | RES0 | SPME | SDD | SPD32 | NSPB | RES0 | TDOSA | TDA | RES0 | TPM | RES0 | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
External Performance Monitors Access Disable. Controls access to Performance Monitor registers by an external debugger.
EPMAD | Meaning |
---|---|
0b0 |
Access to Performance Monitor registers from external debugger is permitted. |
0b1 |
Access to Performance Monitor registers from external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
If the Performance Monitors Extension does not support external debug interface accesses this bit is RES0.
Otherwise, if EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this bit is 0b1.
On a Warm reset, this field resets to 0.
Reserved, RES0.
External Debug Access Disable. Controls access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.
EDAD | Meaning |
---|---|
0b0 |
Access to debug registers, and to OSLAR_EL1 from external debugger is permitted. |
0b1 |
Access to breakpoint and watchpoint registers, and to OSLAR_EL1 from external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b1.
On a Warm reset, this field resets to 0.
External Debug Access disable. Controls access to breakpoint, watchpoint, and optionally OSLAR_EL1 registers by an external debugger.
EDAD | Meaning |
---|---|
0b0 |
Access to debug registers from external debugger is permitted. |
0b1 |
Access to breakpoint and watchpoint registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. It is IMPLEMENTATION DEFINED whether access to the OSLAR_EL1 register from an external debugger is permitted or not permitted. |
If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b1.
On a Warm reset, this field resets to 0.
Reserved, RES0.
Secure Performance Monitors enable. This allows event counting in Secure state.
SPME | Meaning |
---|---|
0b0 |
Event counting prohibited in Secure state. |
0b1 |
Event counting in Secure state not affected by this bit. |
If EL3 is not implemented the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this bit is 0b1.
On a Warm reset, this field resets to 0.
Secure Performance Monitors enable. This allows event counting in Secure state.
SPME | Meaning |
---|---|
0b0 |
Event counting prohibited in Secure state, unless ExternalSecureNoninvasiveDebugEnabled() is TRUE. |
0b1 |
Event counting in Secure state not affected by this bit. |
If EL3 is not implemented the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this bit is 0b1.
On a Warm reset, this field resets to 0.
Reserved, RES0.
AArch64 Secure Self-hosted invasive debug disable. Disables Software debug exceptions in Secure state, other than Breakpoint Instruction exceptions.
SDD | Meaning |
---|---|
0b0 |
Debug exceptions in Secure state are not affected by this bit. |
0b1 |
Debug exceptions, other than Breakpoint Instruction exceptions, are disabled from all Exception levels in Secure state. |
The SDD bit is ignored unless both of the following are true:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
AArch32 Secure self-hosted privileged debug. Enables or disables debug exceptions from Secure EL1 using AArch32, other than Breakpoint Instruction exceptions.
SPD32 | Meaning |
---|---|
0b00 |
Legacy mode. Debug exceptions from Secure EL1 are enabled by the IMPLEMENTATION DEFINED authentication interface. |
0b10 |
Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled. |
0b11 |
Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled. |
Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
This field has no effect on Breakpoint Instruction exceptions. These are always enabled.
This field is:
If Secure EL1 is using AArch32 then:
If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b11.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Non-secure Profiling Buffer. This field controls the owning translation regime and accesses to Statistical Profiling and Profiling Buffer control registers.
NSPB | Meaning |
---|---|
0b00 |
Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in both security states generate Trap exceptions to EL3. |
0b01 |
Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure state generate Trap exceptions to EL3. |
0b10 |
Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in both security states generate Trap exceptions to EL3. |
0b11 |
Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Secure state generate Trap exceptions to EL3. |
The Statistical Profiling and Profiling Buffer control registers trapped by this control are: PMBLIMITR_EL1, PMBPTR_EL1, PMBSR_EL1, PMSCR_EL1, PMSCR_EL2, PMSEVFR_EL1, PMSFCR_EL1, PMSICR_EL1, PMSIDR_EL1, PMSIRR_EL1, and PMSLATFR_EL1.
If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b1, the Effective value of this field is 0b11. If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, the Effective value of this field is 0b01.
On a Warm reset, this field resets to an UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Trap debug OS-related register access. Traps EL2 and EL1 System register accesses to the powerdown debug registers to EL3.
Accesses to the registers are trapped as follows:
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL2 and EL1 System register accesses to the powerdown debug registers are trapped to EL3, unless it is trapped by HDCR.TDOSA or MDCR_EL2.TDOSA. |
The powerdown debug registers are not accessible at EL0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap debug OS-related register access. Traps EL2 and EL1 System register accesses to the powerdown debug registers to EL3.
The following registers are affected by this trap:
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL2 and EL1 System register accesses to the powerdown debug registers are trapped to EL3, unless it is trapped by HDCR.TDOSA or MDCR_EL2.TDOSA. |
The powerdown debug registers are not accessible at EL0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap Debug Access. Traps EL2, EL1, and EL0 System register accesses to those debug System registers that cannot be trapped using the MDCR_EL3.TDOSA field.
Accesses to the debug registers are trapped as follows:
TDA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL0, EL1, and EL2 accesses to the debug registers, other than the registers that can be trapped by MDCR_EL3.TDOSA, are trapped to EL3, from both Security states and both Execution states, unless it is trapped by DBGDSCRext.UDCCdis, MDSCR_EL1.TDCC, HDCR.TDA or MDCR_EL2.TDA. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap Performance Monitor register accesses. Accesses to all Performance Monitor registers from EL0, EL1 and EL2 to EL3, from both Security states and both Execution states are trapped as follows:
TPM | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL2, EL1, and EL0 System register accesses to all Performance Monitor registers are trapped to EL3, unless it is trapped by HDCR.TPM or MDCR_EL2.TPM. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else MDCR_EL3 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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