The EDVIDSR characteristics are:
Contains sampled values captured on reading EDPCSR[31:0].
EDVIDSR is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
This register is present only when ARMv8.0-PCSample is implemented and ARMv8.2-PCSample is not implemented. Otherwise, direct accesses to EDVIDSR are RES0.
Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.
When the PC Sample-based Profiling Extension is implemented in the external debug registers space, if EL2 is not implemented and EL3 is not implemented, it is IMPLEMENTATION DEFINED whether EDVIDSR is implemented.
ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.
If ARMv8.1-VHE is implemented, the format of this register differs depending on the value of EDSCR.SC2.
The EDVIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS | E2 | E3 | HV | RES0 | VMID[15:8] | VMID |
This format applies in all Armv8.0 implementations.
Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.
If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.
NS | Meaning |
---|---|
0b0 |
Sample is from Secure state. |
0b1 |
Sample is from Non-secure state. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.
E2 | Meaning |
---|---|
0b0 |
Sample is not from EL2. |
0b1 |
Sample is from EL2. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.
E3 | Meaning |
---|---|
0b0 |
Sample is not from EL3 using AArch64. |
0b1 |
Sample is from EL3 using AArch64. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:
HV | Meaning |
---|---|
0b0 |
Bits[63:32] of the most recent EDPCSR sample are zero. |
0b1 |
Bits[63:32] of the most recent EDPCSR sample might be nonzero. |
An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero. An EDVIDSR.HV value of 0 is a hint that EDPCSRhi (EDPCSR[63:32]) does not need to be read.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Extension to VMID[7:0]. See VMID[7:0] for more details.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample. When the most recent EDPCSR sample was generated:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL2 |
Context ID. The value of CONTEXTIDR_EL2 that is associated with the most recent EDPCSR sample. When the most recent EDPCSR sample was generated:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance |
---|---|---|
Debug | 0x0A8 | EDVIDSR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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