The PMCIDR1 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Component Identification scheme'.
It is IMPLEMENTATION DEFINED whether PMCIDR1 is implemented in the Core power domain or in the Debug power domain.
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMCIDR1 is a 32-bit register.
The PMCIDR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class. Reads as 0x9, debug component.
Preamble. RAZ.
Component | Offset | Instance |
---|---|---|
PMU | 0xFF4 | PMCIDR1 |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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