The EDPIDR4 characteristics are:
Provides information to identify an external debug component.
For more information, see 'About the Peripheral identification scheme'.
It is IMPLEMENTATION DEFINED whether EDPIDR4 is implemented in the Core power domain or in the Debug power domain.
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
EDPIDR4 is a 32-bit register.
The EDPIDR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.
Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.
Component | Offset | Instance |
---|---|---|
Debug | 0xFD0 | EDPIDR4 |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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