The EDSCR2 characteristics are:
Extended control register for the debug implementation
External register EDSCR2 is architecturally mapped to AArch64 System register CDBGDTR_EL0[128] .
EDSCR2 is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
This register is present only when Morello is implemented. Otherwise, direct accesses to EDSCR2 are RES0.
EDSCR2 is a 32-bit register.
The EDSCR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CE | DTRTAG |
Reserved, RES0.
Access to Morello Feature status. In Debug state, each bit gives the current access to the Morello architecture extension at each Exception level as controlled by CPTR_ELx and CPACR_EL1:
CE | Meaning |
---|---|
0b1111 |
All Exception levels have access to the Morello architecture extension or the PE is in Non-debug state. |
0b1110 |
The PE is in Debug state. EL0 does not have access to the Morello architecture extension. All other Exception levels have access to the Morello architecture extension. |
0b1100 |
The PE is in Debug state. EL0 and EL1 do not have access to the Morello architecture extension. All other Exception levels have access to the Morello architecture extension. |
0b1000 |
The PE is in Debug state. EL3 has access to the Morello architecture extension. All other Exception levels do not have access to the Morello architecture extension. |
0b0000 |
The PE is in Debug state. No Exception level has access to the Morello architecture extension. |
In Non-debug state, this field is RAO.
Access to this field is RO.
Capability data transfer register tag.
On a Cold reset, this field resets to an UNKNOWN value.
Access to EDSCR2 is only possible externally
Component | Offset | Instance |
---|---|---|
Debug | 0x048 | EDSCR2 |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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