The EDSCR characteristics are:
Main control register for the debug implementation.
External register EDSCR bits [30:29] are architecturally mapped to AArch64 System register MDCCSR_EL0[30:29] .
EDSCR is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
EDSCR is a 32-bit register.
The EDSCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | RXfull | TXfull | ITO | RXO | TXU | PipeAdv | ITE | INTdis | TDA | MA | SC2 | NS | RES0 | SDD | RES0 | HDE | RW | EL | A | ERR | STATUS |
Reserved, RES0.
DTRRX full.
On a Cold reset, this field resets to 0.
Access to this field is RO.
DTRTX full.
On a Cold reset, this field resets to 0.
Access to this field is RO.
ITR overrun.
If the PE is in Non-debug state, this bit is UNKNOWN. ITO is set to 0 on entry to Debug state.
Access to this field is RO.
DTRRX overrun.
On a Cold reset, this field resets to 0.
Access to this field is RO.
DTRTX underrun.
On a Cold reset, this field resets to 0.
Access to this field is RO.
Pipeline advance. Set to 1 every time the PE pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
Access to this field is RO.
ITR empty.
If the PE is in Non-debug state, this bit is UNKNOWN. It is always valid in Debug state.
Access to this field is RO.
Interrupt disable.
When OSLSR_EL1.OSLK == 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
INTdis | Meaning |
---|---|
0b00 |
Do not disable interrupts. |
0b01 |
Disable interrupts taken to Non-secure EL1. |
0b10 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If ExternalSecureInvasiveDebugEnabled() == TRUE, also disable interrupts taken to Secure EL1. |
0b11 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If ExternalSecureInvasiveDebugEnabled() == TRUE, also disable all other interrupts. |
On a Cold reset, this field resets to 0.
Traps accesses to the following debug System registers:
The possible values of this field are:
TDA | Meaning |
---|---|
0b0 |
Accesses to debug System registers do not generate a Software Access Debug event. |
0b1 |
Accesses to debug System registers generate a Software Access Debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed. |
On a Cold reset, this field resets to 0.
Memory access mode. Controls the use of memory-access mode for accessing ITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.
Possible values of this field are:
MA | Meaning |
---|---|
0b0 |
Normal access mode. |
0b1 |
Memory access mode. |
On a Cold reset, this field resets to 0.
Sample CONTEXTIDR_EL2. Controls whether the PC Sample-based Profiling Extension samples CONTEXTIDR_EL2 or VTTBR_EL2.VMID.
SC2 | Meaning |
---|---|
0b0 |
Sample VTTBR_EL2.VMID. |
0b1 |
Sample CONTEXTIDR_EL2. |
On a Cold reset, this field resets to 0.
Reserved, RES0.
Non-secure status. When in Debug state, gives the current Security state:
NS | Meaning |
---|---|
0b0 |
Secure state, IsSecure() == TRUE. |
0b1 |
Non-secure state, IsSecure() == FALSE. |
In Non-debug state, this bit is UNKNOWN.
Access to this field is RO.
Reserved, RES0.
Secure debug disabled.
On entry to Debug state:
In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.
In Non-debug state:
If EL3 is not implemented and the implementation is Non-secure, this bit is RES1.
Access to this field is RO.
Reserved, RES0.
Halting debug enable. The possible values of this field are:
HDE | Meaning |
---|---|
0b0 |
Halting disabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
0b1 |
Halting enabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
On a Cold reset, this field resets to 0.
Exception level Execution state status. In Debug state, each bit gives the current Execution state of each Exception level:
RW | Meaning |
---|---|
0b1111 |
All Exception levels are using AArch64 or the PE is in Non-debug state. |
0b1110 |
The PE is in Debug state. EL0 is using AArch32. All other Exception levels are using AArch64. Only permitted if the PE is executing at EL0. |
0b110x |
The PE is in Debug state. EL0 and EL1 are using AArch32. EL2 and EL3 are using AArch64. Only permitted if EL2 is implemented and enabled in the current Security state. |
0b10xx |
The PE is in Debug state. EL0, EL1, and, if implemented in the current Security state, EL2 are using AArch32. EL3 is using AArch64. Only permitted if EL3 is implemented. |
0b0xxx |
The PE is in Debug state. All Exception levels are using AArch32. |
In Non-debug state, this field is RAO.
Access to this field is RO.
Exception level. In Debug state, this gives the current EL of the PE.
In Non-debug state, this field is RAZ.
Access to this field is RO.
SError interrupt pending. In Debug state, indicates whether an SError interrupt is pending:
A | Meaning |
---|---|
0b0 |
No SError interrupt pending. |
0b1 |
SError interrupt pending. |
A debugger can read EDSCR to check whether an SError interrupt is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.
UNKNOWN in Non-debug state.
Access to this field is RO.
Cumulative error flag. This bit is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
On a Cold reset, this field resets to 0.
Access to this field is RO.
Debug status flags.
STATUS | Meaning |
---|---|
0b000001 |
PE is restarting, exiting Debug state. |
0b000010 |
PE is in Non-debug state. |
0b000111 |
Breakpoint. |
0b010011 |
External debug request. |
0b011011 |
Halting step, normal. |
0b011111 |
Halting step, exclusive. |
0b100011 |
OS Unlock Catch. |
0b100111 |
Reset Catch. |
0b101011 |
Watchpoint. |
0b101111 |
HLT instruction. |
0b110011 |
Software access to debug register. |
0b110111 |
Exception Catch. |
0b111011 |
Halting step, no syndrome. |
All other values of STATUS are reserved.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0x088 | EDSCR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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