The CTIPIDR4 characteristics are:
Provides information to identify a CTI component.
For more information, see 'About the Peripheral identification scheme'.
CTIPIDR4 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR4 is a 32-bit register.
The CTIPIDR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.
Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.
Component | Offset | Instance |
---|---|---|
CTI | 0xFD0 | CTIPIDR4 |
Accesses on this interface are RO.
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.