The ICC_IGRPEN1_EL1 characteristics are:
Controls whether Group 1 interrupts are enabled for the current Security state.
AArch64 System register ICC_IGRPEN1_EL1 bits [31:0] (S) are architecturally mapped to AArch32 System register ICC_IGRPEN1[31:0] (S) .
AArch64 System register ICC_IGRPEN1_EL1 bits [31:0] (NS) are architecturally mapped to AArch32 System register ICC_IGRPEN1[31:0] (NS) .
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
ICC_IGRPEN1_EL1 is a 64-bit register.
The ICC_IGRPEN1_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | Enable | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Enables Group 1 interrupts for the current Security state.
Enable | Meaning |
---|---|
0b0 |
Group 1 interrupts are disabled for the current Security state. |
0b1 |
Group 1 interrupts are enabled for the current Security state. |
Virtual accesses to this register update ICH_VMCR_EL2.VENG1.
If EL3 is present:
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
This field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b1100 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then return ICV_IGRPEN1_EL1; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_IGRPEN1_EL1_S; else return ICC_IGRPEN1_EL1_NS; else return ICC_IGRPEN1_EL1; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_IGRPEN1_EL1_S; else return ICC_IGRPEN1_EL1_NS; else return ICC_IGRPEN1_EL1; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then return ICC_IGRPEN1_EL1_S; else return ICC_IGRPEN1_EL1_NS;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b1100 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_IGRPEN1_EL1 = X[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_IGRPEN1_EL1_S = X[t]; else ICC_IGRPEN1_EL1_NS = X[t]; else ICC_IGRPEN1_EL1 = X[t]; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_IGRPEN1_EL1_S = X[t]; else ICC_IGRPEN1_EL1_NS = X[t]; else ICC_IGRPEN1_EL1 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then ICC_IGRPEN1_EL1_S = X[t]; else ICC_IGRPEN1_EL1_NS = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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