The SCTLR_EL3 characteristics are:
Provides top level control of the system, including its memory system, at EL3.
This register is present only when HaveEL(EL3). Otherwise, direct accesses to SCTLR_EL3 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
SCTLR_EL3 is a 64-bit register.
The SCTLR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | DSSBS | RES0 | |||||||||||||||||||||||||||||
RES0 | RES1 | RES0 | EE | RES0 | RES1 | IESB | RES0 | WXN | RES1 | RES0 | RES1 | RES0 | I | RES1 | RES0 | RES1 | SA | C | A | M | |||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Default PSTATE.SSBS value on Exception Entry.
DSSBS | Meaning |
---|---|
0b0 |
PSTATE.SSBS is set to 0 on an exception to EL3 |
0b1 |
PSTATE.SSBS is set to 1 on an exception to EL3 |
In a system where the PE resets into EL3, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime.
EE | Meaning |
---|---|
0b0 |
Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are little-endian. |
0b1 |
Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are big-endian. |
If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES0.
If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES1.
The EE bit is permitted to be cached in a TLB.
In a system where the PE resets into EL3, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES1.
Implicit Error Synchronization event enable.
IESB | Meaning |
---|---|
0b0 |
Disabled. |
0b1 |
An implicit error synchronization event is added:
|
When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event is added after each DCPSx instruction taken to EL3 and before each DRPS instruction executed at EL3, in addition to the other cases where it is added.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:
WXN | Meaning |
---|---|
0b0 |
This control has no effect on memory access permissions. |
0b1 |
Any region that is writable in the EL3 translation regime is forced to XN for accesses from software executing at EL3. |
This bit applies only when SCTLR_EL3.M bit is set.
The WXN bit is permitted to be cached in a TLB.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Instruction access Cacheability control, for accesses at EL3:
I | Meaning |
---|---|
0b0 |
All instruction access to Normal memory from EL3 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. |
0b1 |
This control has no effect on the Cacheability of instruction access to Normal memory from EL3. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. |
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
In a system where the PE resets into EL3, this field resets to 0.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Cacheability control, for data accesses.
C | Meaning |
---|---|
0b0 |
All data access to Normal memory from EL3, and all Normal memory accesses to the EL3 translation tables, are Non-cacheable for all levels of data and unified cache. |
0b1 |
This control has no effect on the Cacheability of:
|
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
In a system where the PE resets into EL3, this field resets to 0.
Alignment check enable. This is the enable bit for Alignment fault checking at EL3.
A | Meaning |
---|---|
0b0 |
Alignment fault checking disabled when executing at EL3. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed. |
0b1 |
Alignment fault checking enabled when executing at EL3. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. |
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
MMU enable for EL3 stage 1 address translation. Possible values of this bit are:
M | Meaning |
---|---|
0b0 |
EL3 stage 1 address translation disabled. See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory. |
0b1 |
EL3 stage 1 address translation enabled. |
In a system where the PE resets into EL3, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return SCTLR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR_EL3 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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