The SCTLR_EL2 characteristics are:
Provides top level control of the system, including its memory system, at EL2.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, these controls apply also to execution at EL0.
AArch64 System register SCTLR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HSCTLR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
SCTLR_EL2 is a 64-bit register.
The SCTLR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | DSSBS | RES0 | |||||||||||||||||||||||||||||
RES0 | RES1 | RES0 | EE | RES0 | RES1 | IESB | RES0 | WXN | RES1 | RES0 | RES1 | RES0 | I | RES1 | RES0 | RES1 | SA | C | A | M | |||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
This format applies in all Armv8.0 implementations, and from Armv8.1 when the Effective value of HCR_EL2.{E2H, TGE} != {1, 1}.
Reserved, RES0.
Default PSTATE.SSBS value on Exception Entry.
DSSBS | Meaning |
---|---|
0b0 |
PSTATE.SSBS is set to 0 on an exception to EL2. |
0b1 |
PSTATE.SSBS is set to 1 on an exception to EL2. |
In a system where the PE resets into EL2, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Endianness of data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL1&0 translation regime.
The possible values of this bit are:
EE | Meaning |
---|---|
0b0 |
Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL1&0 translation regime are little-endian. |
0b1 |
Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL1&0 translation regime are big-endian. |
If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES0.
If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES1.
The EE bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES1.
Implicit Error Synchronization event enable.
IESB | Meaning |
---|---|
0b0 |
Disabled. |
0b1 |
An implicit error synchronization event is added:
|
When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event is added after each DCPSx instruction taken to EL2 and before each DRPS instruction executed at EL2, in addition to the other cases where it is added.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Write permission implies XN (Execute-never). For the EL2 or EL2&0 translation regime, this bit can force all memory regions that are writable to be treated as XN:
WXN | Meaning |
---|---|
0b0 |
This control has no effect on memory access permissions. |
0b1 |
Any region that is writable in the EL2 or EL2&0 translation regime is forced to XN for accesses from software executing at EL2. |
This bit applies only when SCTLR_EL2.M bit is set.
The WXN bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Instruction access Cacheability control, for accesses at EL2:
I | Meaning |
---|---|
0b0 |
All instruction access to Normal memory from EL2 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. |
0b1 |
This control has no effect on the Cacheability of instruction access to Normal memory from EL2. If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. |
This bit has no effect on the EL1&0 or EL3 translation regimes.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL2 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Cacheability control, for data accesses.
C | Meaning |
---|---|
0b0 |
All data access to Normal memory from EL2, and all Normal memory accesses to the EL2 translation tables, are Non-cacheable for all levels of data and unified cache. |
0b1 |
This control has no effect on the Cacheability of:
|
This bit has no effect on the EL1&0 or EL3 translation regimes.
In a system where the PE resets into EL2, this field resets to 0.
Alignment check enable. This is the enable bit for Alignment fault checking at EL2:
A | Meaning |
---|---|
0b0 |
Alignment fault checking disabled when executing at EL2. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed. |
0b1 |
Alignment fault checking enabled when executing at EL2. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. |
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
MMU enable for EL2 stage 1 address translation. Possible values of this bit are:
M | Meaning |
---|---|
0b0 |
EL2 stage 1 address translation disabled. See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory. |
0b1 |
EL2 stage 1 address translation enabled. |
In a system where the PE resets into EL2, this field resets to 0.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | DSSBS | RES0 | |||||||||||||||||||||||||||||
RES0 | LSMAOE | nTLSMD | RES0 | UCI | EE | E0E | SPAN | RES1 | IESB | TSCXT | WXN | nTWE | RES0 | nTWI | UCT | DZE | RES0 | I | RES1 | EnRCTX | RES0 | SED | ITD | RES0 | CP15BEN | SA0 | SA | C | A | M | |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
This format applies only from Armv8.1 when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}.
Reserved, RES0.
Default PSTATE.SSBS value on Exception Entry.
DSSBS | Meaning |
---|---|
0b0 |
PSTATE.SSBS is set to 0 on an exception to EL2. |
0b1 |
PSTATE.SSBS is set to 1 on an exception to EL2. |
In a system where the PE resets into EL2, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES0.
Load Multiple and Store Multiple Atomicity and Ordering Enable.
LSMAOE | Meaning |
---|---|
0b0 |
For all memory accesses at EL0, A32 and T32 Load Multiple and Store Multiple can have an interrupt taken during the sequence memory accesses, and the memory accesses are not required to be ordered. |
0b1 |
The ordering and interrupt behavior of A32 and T32 Load Multiple and Store Multiple at EL0 is as defined for Armv8.0. |
This bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory.
nTLSMD | Meaning |
---|---|
0b0 |
All memory accesses by A32 and T32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are trapped and generate a stage 1 Alignment fault. |
0b1 |
All memory accesses by A32 and T32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are not trapped. |
This bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Reserved, RES0.
Traps EL0 execution of cache maintenance instructions to EL2, from AArch64 state only. This applies to DC CVAU, DC CIVAC, DC CVAC, DC CVAP, and IC IVAU.
If ARMv8.2-DCCVADP is implemented, this trap also applies to DC CVADP.
UCI | Meaning |
---|---|
0b0 |
Any attempt to execute an instruction that this trap applies to at EL0 using AArch64 is trapped to EL2. |
0b1 |
This control does not cause any instructions to be trapped. |
If the Point of Coherency is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean, or clean and invalidate instruction that operates by VA to the point of coherency can be trapped when the value of this control is 1.
If the Point of Unification is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean by VA to the Point of Unification instruction can be trapped when the value of this control is 1.
If the Point of Unification is before any level of instruction cache, it is IMPLEMENTATION DEFINED whether the execution of any instruction cache invalidate by VA to the Point of Unification instruction can be trapped when the value of this control is 1.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Endianness of data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL2&0 translation regime.
The possible values of this bit are:
EE | Meaning |
---|---|
0b0 |
Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL2&0 translation regime are little-endian. |
0b1 |
Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL2&0 translation regime are big-endian. |
If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES0.
If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES1.
The EE bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an IMPLEMENTATION DEFINED value.
Endianness of data accesses at EL0.
E0E | Meaning |
---|---|
0b0 |
Explicit data accesses at EL0 are little-endian. |
0b1 |
Explicit data accesses at EL0 are big-endian. |
If an implementation only supports Little-endian accesses at EL0 then this bit is RES0. This option is not permitted when SCTLR_EL1.EE is RES1.
If an implementation only supports Big-endian accesses at EL0 then this bit is RES1. This option is not permitted when SCTLR_EL1.EE is RES0.
This bit has no effect on the endianness of LDTR, LDTRH, LDTRSH, LDTRSW, STTR, and STTRH instructions executed at EL1.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Set Privileged Access Never, on taking an exception to EL2.
SPAN | Meaning |
---|---|
0b0 |
PSTATE.PAN is set to 1 on taking an exception to EL2. |
0b1 |
The value of PSTATE.PAN is left unchanged on taking an exception to EL2. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Implicit Error Synchronization event Enable.
IESB | Meaning |
---|---|
0b0 |
Disabled. |
0b1 |
An implicit error synchronization event is added:
|
When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event is added after each DCPSx instruction taken to EL2 and before each DRPS instruction executed at EL2, in addition to the other cases where it is added.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap EL0 Access to the SCXTNUM_EL0 register, when EL0 is using AArch64.
TSCXT | Meaning |
---|---|
0b0 |
EL0 access to SCXTNUM_EL0 is not disabled by this mechanism. |
0b1 |
EL0 access to SCXTNUM_EL0 is disabled, causing an exception to EL2, and the SCXTNUM_EL0 value is treated at 0. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Write permission implies XN (Execute-never). For the EL2 or EL2&0 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:
WXN | Meaning |
---|---|
0b0 |
This control has no effect on memory access permissions. |
0b1 |
Any region that is writable in the EL2 or EL2&0 translation regime is forced to XN for accesses from software executing at EL2. |
This bit applies only when SCTLR_EL2.M bit is set.
The WXN bit is permitted to be cached in a TLB.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Traps EL0 execution of WFE instructions to EL2, from both Execution states.
nTWE | Meaning |
---|---|
0b0 |
Any attempt to execute a WFE instruction at EL0 is trapped to EL2, if the instruction would otherwise have caused the PE to enter a low-power state. |
0b1 |
This control does not cause any instructions to be trapped. |
In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps EL0 execution of WFI instructions to EL2, from both Execution states.
nTWI | Meaning |
---|---|
0b0 |
Any attempt to execute a WFI instruction at EL0 is trapped EL2, if the instruction would otherwise have caused the PE to enter a low-power state. |
0b1 |
This control does not cause any instructions to be trapped. |
In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Traps EL0 accesses to the CTR_EL0 to EL2, from AArch64 state only.
UCT | Meaning |
---|---|
0b0 |
Accesses to the CTR_EL0 from EL0 using AArch64 are trapped to EL2. |
0b1 |
This control does not cause any instructions to be trapped. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Traps EL0 execution of DC ZVA instructions to EL2, from AArch64 state only.
DZE | Meaning |
---|---|
0b0 |
Any attempt to execute an instruction that this trap applies to at EL0 using AArch64 is trapped to EL2. Reading DCZID_EL0.DZP from EL0 returns 1, indicating that the instructions that this trap applies to are not supported. |
0b1 |
This control does not cause any instructions to be trapped. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Instruction access Cacheability control, for accesses at EL2 and EL0:
I | Meaning |
---|---|
0b0 |
All instruction access to Normal memory from EL2 and EL0 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2&0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. |
0b1 |
This control has no effect on the Cacheability of instruction access to Normal memory from EL2 and EL0. If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. |
This bit has no effect on the EL3 translation regimes.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES1.
Enable EL0 Access to the AArch32 CFPRCTX, DVPRCTX and CPPRCTX instructions, and the AArch64 CFP RCTX, DVP RCT and CPP RCTX System instructions.
EnRCTX | Meaning |
---|---|
0b0 |
EL0 access to these instructions is disabled, and these instructions are trapped to EL1. |
0b1 |
EL0 access to these instructions is enabled. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
SETEND instruction disable. Disables SETEND instructions at EL0 using AArch32.
SED | Meaning |
---|---|
0b0 |
SETEND instruction execution is enabled at EL0 using AArch32. |
0b1 |
SETEND instructions are UNDEFINED at EL0 using AArch32. |
If the implementation does not support mixed-endian operation at any Exception level, this bit is RES1.
If EL0 cannot use AArch32, this bit is RES1.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
IT Disable. Disables some uses of IT instructions at EL0 using AArch32.
ITD | Meaning |
---|---|
0b0 |
All IT instruction functionality is enabled at EL0 using AArch32. |
0b1 |
Any attempt at EL0 using AArch32 to execute any of the following is UNDEFINED:
These instructions are always UNDEFINED, regardless of whether they would pass or fail the condition code check that applies to them as a result of being in an IT block. It is IMPLEMENTATION DEFINED whether the IT instruction is treated as:
This means that, for the situations that are UNDEFINED, either the second 16-bit instruction or the 32-bit instruction is UNDEFINED. An implementation might vary dynamically as to whether IT is treated as a 16-bit instruction or the first half of a 32-bit instruction. |
If an instruction in an active IT block that would be disabled by this field sets this field to 1 then behavior is CONSTRAINED UNPREDICTABLE. For more information see 'Changes to an ITD control by an instruction in an IT block' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section E1.2.4
If EL0 cannot use AArch32, this bit is RES1.
ITD is optional, but if it is implemented in the SCTLR then it must also be implemented in the SCTLR_EL1. If it is not implemented then this bit is RAZ/WI.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==0b1111) encoding space from EL0:
CP15BEN | Meaning |
---|---|
0b0 |
EL0 using AArch32: EL0 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is UNDEFINED. |
0b1 |
EL0 using AArch32: EL0 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is enabled. |
If EL0 cannot use AArch32, this bit is RES0.
CP15BEN is optional, but if it is implemented in the SCTLR then it must also be implemented in the SCTLR_EL1. If it is not implemented then this bit is RAO/WI.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
SP Alignment check enable for EL0. When set to 1, if a load or store instruction executed at EL0 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL2 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Cacheability control, for data accesses.
C | Meaning |
---|---|
0b0 |
All data access to Normal memory from EL2 and EL0, and all Normal memory accesses to the EL2&0 translation tables, are Non-cacheable for all levels of data and unified cache. |
0b1 |
This control has no effect on the Cacheability of:
|
This bit has no effect on the EL3 translation regimes.
In a system where the PE resets into EL2, this field resets to 0.
Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and EL0.
A | Meaning |
---|---|
0b0 |
Alignment fault checking disabled when executing at EL2 and EL0. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed. |
0b1 |
Alignment fault checking enabled when executing at EL2 and EL0. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. |
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
MMU enable for EL2&0 stage 1 address translation. Possible values of this bit are:
M | Meaning |
---|---|
0b0 |
EL2&0 stage 1 address translation disabled. See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory. |
0b1 |
EL2&0 stage 1 address translation enabled. |
In a system where the PE resets into EL2, this field resets to 0.
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic SCTLR_EL2 or SCTLR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); else return SCTLR_EL2; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return SCTLR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR_EL2 = X[t];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return SCTLR_EL1; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return SCTLR_EL2; else return SCTLR_EL1; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return SCTLR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else SCTLR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then SCTLR_EL2 = X[t]; else SCTLR_EL1 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR_EL1 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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