The CTICLAIMCLR characteristics are:
Used by software to read the values of the CLAIM bits, and to clear CLAIM tag bits to 0.
CTICLAIMCLR is in the Debug power domain. Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
Implementation of this register is OPTIONAL.
CTICLAIMCLR is a 32-bit register.
The CTICLAIMCLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAIM[<x>], bit [x] |
CLAIM tag clear bit.
For values of x greater than or equal to the IMPLEMENTATION DEFINED number of CLAIM tags, this bit is RAZ/SBZ. Software can rely on these bits reading as zero, and must use a Should-Be-Zero policy on writes. Implementations must ignore writes.
For other values of x, reads return the value of CLAIM[x] and the behavior on writes is:
CLAIM[<x>] | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Indirectly clear CLAIM[x] to 0. |
A single write to CTICLAIMCLR can clear multiple tags to 0.
An External Debug reset clears the CLAIM tag bits to 0.
Component | Offset | Instance |
---|---|---|
CTI | 0xFA4 | CTICLAIMCLR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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