The TPIDRRO_EL0 characteristics are:
Provides a location where software executing at EL1 or higher can store thread identifying information that is visible to software executing at EL0, for OS management purposes.
The PE makes no use of this register.
AArch64 System register TPIDRRO_EL0 bits [31:0] are architecturally mapped to AArch32 System register TPIDRURO[31:0] .
RW fields in this register reset to architecturally UNKNOWN values.
TPIDRRO_EL0 is a 129-bit register.
The TPIDRRO_EL0 bit assignments are:
Thread ID. Thread identifying information stored by software running at this Exception level
This field resets to an architecturally UNKNOWN value.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Thread ID | |||||||||||||||||||||||||||||||
Thread ID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Thread ID. Thread identifying information stored by software running at this Exception level.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then return TPIDRRO_EL0<63:0>; elsif PSTATE.EL == EL1 then return TPIDRRO_EL0<63:0>; elsif PSTATE.EL == EL2 then return TPIDRRO_EL0<63:0>; elsif PSTATE.EL == EL3 then return TPIDRRO_EL0<63:0>;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then TPIDRRO_EL0 = ZeroExtend(X[t]); elsif PSTATE.EL == EL2 then TPIDRRO_EL0 = ZeroExtend(X[t]); elsif PSTATE.EL == EL3 then TPIDRRO_EL0 = ZeroExtend(X[t]);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.CEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x29); else AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.CEN != '11' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return TPIDRRO_EL0; elsif PSTATE.EL == EL1 then if CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return TPIDRRO_EL0; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return TPIDRRO_EL0; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return TPIDRRO_EL0;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1101 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else TPIDRRO_EL0 = C[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else TPIDRRO_EL0 = C[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else TPIDRRO_EL0 = C[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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