VBAR_EL3, Vector Base Address Register (EL3)

The VBAR_EL3 characteristics are:

Purpose

Holds the vector base address for any exception that is taken to EL3.

Configuration

This register is present only when HaveEL(EL3). Otherwise, direct accesses to VBAR_EL3 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VBAR_EL3 is a 129-bit register.

Field descriptions

The VBAR_EL3 bit assignments are:

When Morello is implemented and Capability access at EL3 is not trapped:

Bits [128:0]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL3.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

Bits [10:0] are treated as 0 for the purpose of calculating the exception vector address.

This field resets to an architecturally UNKNOWN value.

When Morello is implemented and Capability access at EL3 is trapped:

Bits [128:64]

Reserved, RES0.

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL3.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

This field resets to an architecturally UNKNOWN value.

Bits [10:0]

Reserved, RES0.

When Morello is not implemented:

6362616059585756555453525150494847464544434241403938373635343332
Vector Base Address
Vector Base AddressRES0
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL3.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

This field resets to an architecturally UNKNOWN value.

Bits [10:0]

Reserved, RES0.

Accessing the VBAR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, VBAR_EL3

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return VBAR_EL3<63:0>;

MSR VBAR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else VBAR_EL3 = ZeroExtend(X[t]);

MRS <Ct>, CVBAR_EL3

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x2A); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return VBAR_EL3;

MSR CVBAR_EL3, <Ct>

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x2A); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else VBAR_EL3 = C[t];




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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