The GICC_PMR characteristics are:
This register provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Higher interrupt priority corresponds to a lower value of the Priority field.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICC_PMR is a 32-bit register.
The GICC_PMR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Priority |
Reserved, RES0.
The priority mask level for the CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows:
For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
This field resets to an architecturally UNKNOWN value.
If the GIC implementation supports two Security states:
For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x0004 | GICC_PMR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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