The SCR_EL3 characteristics are:
Defines the configuration of the current Security state. It specifies:
AArch64 System register SCR_EL3 bits [31:0] can be mapped to AArch32 System register SCR[31:0] , but this is not architecturally mandated.
This register is present only when HaveEL(EL3). Otherwise, direct accesses to SCR_EL3 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
SCR_EL3 is a 64-bit register.
The SCR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | EnSCXT | RES0 | TERR | TLOR | TWE | TWI | ST | RW | SIF | HCE | SMD | RES0 | RES1 | EA | FIQ | IRQ | NS | ||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Enable access to the SCXTNUM_EL2, SCXTNUM_EL1, and SCXTNUM_EL0 registers. The defined values are:
EnSCXT | Meaning |
---|---|
0b0 |
EL2, EL1 and EL0 access to SCXTNUM_EL0, EL2 and EL1 access to SCXTNUM_EL1, EL2 access to SCXTNUM_EL2 registers are disabled by this mechanism, causing an exception to EL3, and the values of these registers to be treated as 0. |
0b1 |
This control does not cause accesses to SCXTNUM_EL0, SCXTNUM_EL1, SCXTNUM_EL2 to be trapped. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Trap Error record accesses. Accesses to the RAS ERR and RAS ERX registers from EL1 and EL2 to EL3 are trapped as follows:
If EL1 is using AArch64, ERRIDR_EL1, ERRSELR_EL1, ERXADDR_EL1, ERXCTLR_EL1, ERXFR_EL1, ERXMISC0_EL1, ERXMISC1_EL1, and ERXSTATUS_EL1, are trapped and reported using EC syndrome value 0x18.
If EL1 is using AArch32, accesses by MCR or MRC to the following registers are reported using EC syndrome value 0x03, accesses by MCRR or MRRC are reported using EC syndrome value 0x04:
TERR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Accesses to the specified registers from EL1 and EL2 generate a Trap exception to EL3. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap LOR registers. Traps accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from EL1 and EL2 to EL3, unless the access has been trapped to EL2.
TLOR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 and EL2 accesses to the LOR registers that are not UNDEFINED are trapped to EL3, unless it is trapped HCR_EL2.TLOR. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps EL2, EL1, and EL0 execution of WFE instructions to EL3, from both Security states and both Execution states, reported using EC syndrome value 0x01.
TWE | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt to execute a WFE instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWE, HCR.TWE, SCTLR_EL1.nTWE, SCTLR_EL2.nTWE, or HCR_EL2.TWE. |
In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
For more information about when WFE instructions can cause the PE to enter a low-power state, see 'Wait for Event mechanism and Send event'.
This field resets to an architecturally UNKNOWN value.
Traps EL2, EL1, and EL0 execution of WFI instructions to EL3, from both Security states and both Execution states, reported using EC syndrome value 0x01.
TWI | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt to execute a WFI instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWI, HCR.TWI, SCTLR_EL1.nTWI, SCTLR_EL2.nTWI, or HCR_EL2.TWI. |
In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
For more information about when WFI instructions can cause the PE to enter a low-power state, see 'Wait for Interrupt'.
This field resets to an architecturally UNKNOWN value.
Traps Secure EL1 accesses to the Counter-timer Physical Secure timer registers to EL3, from AArch64 state only, reported using EC syndrome value 0x18.
ST | Meaning |
---|---|
0b0 |
Secure EL1 using AArch64 accesses to the CNTPS_TVAL_EL1, CNTPS_CTL_EL1, and CNTPS_CVAL_EL1 are trapped to EL3 when Secure EL2 is disabled. If Secure EL2 is enabled, the behavior is as if the value of this field was 0b1. |
0b1 |
This control does not cause any instructions to be trapped. |
Accesses to the Counter-timer Physical Secure timer registers are always enabled at EL3. These registers are not accessible at EL0.
This field resets to an architecturally UNKNOWN value.
Execution state control for lower Exception levels.
RW | Meaning |
---|---|
0b0 |
Lower levels are all AArch32. |
0b1 |
The next lower level is AArch64. If EL2 is present:
If EL2 is not present:
|
If AArch32 state is not supported by the implementation at EL2 and AArch32 state is not supported by the implementation at EL1, then this bit is RAO/WI.
If AArch32 state is supported by the implementation at EL1, SCR_EL3.NS == 1 and AArch32 state is not supported by the implementation at EL2, the Effective value of this bit is 1.
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Secure instruction fetch. When the PE is in Secure state, this bit disables instruction fetch from Non-secure memory.
SIF | Meaning |
---|---|
0b0 |
Secure state instruction fetches from Non-secure memory are permitted. |
0b1 |
Secure state instruction fetches from Non-secure memory are not permitted. |
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Hypervisor Call instruction enable. Enables HVC instructions at EL3 and, if EL2 is enabled in the current Security state, at EL2 and EL1, in both Execution states, reported using EC syndrome value 0x00.
HCE | Meaning |
---|---|
0b0 |
HVC instructions are UNDEFINED. |
0b1 |
HVC instructions are enabled at EL3, EL2, and EL1. |
HVC instructions are always UNDEFINED at EL0 and, if Secure EL2 is disabled, at Secure EL1. Any resulting exception is taken from the current Exception level to the current Exception level.
If EL2 is not implemented, this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Secure Monitor Call disable. Disables SMC instructions at EL1 and above, from both Security states and both Execution states, reported using EC syndrome value 0x00.
SMD | Meaning |
---|---|
0b0 |
SMC instructions are enabled at EL3, EL2 and EL1. |
0b1 |
SMC instructions are UNDEFINED. |
SMC instructions are always UNDEFINED at EL0. Any resulting exception is taken from the current Exception level to the current Exception level.
If HCR_EL2.TSC or HCR.TSC traps attempted EL1 execution of SMC instructions to EL2, that trap has priority over this disable.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES1.
External Abort and SError interrupt routing.
EA | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL3, External aborts and SError interrupts are not taken to EL3. In addition, when executing at EL3:
|
0b1 |
When executing at any Exception level, External aborts and SError interrupts are taken to EL3. |
For more information, see 'Asynchronous exception routing' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).
This field resets to an architecturally UNKNOWN value.
Physical FIQ Routing.
FIQ | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL3, physical FIQ interrupts are not taken to EL3. When executing at EL3, physical FIQ interrupts are not taken. |
0b1 |
When executing at any Exception level, physical FIQ interrupts are taken to EL3. |
For more information, see 'Asynchronous exception routing' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.
This field resets to an architecturally UNKNOWN value.
Physical IRQ Routing.
IRQ | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL3, physical IRQ interrupts are not taken to EL3. When executing at EL3, physical IRQ interrupts are not taken. |
0b1 |
When executing at any Exception level, physical IRQ interrupts are taken to EL3. |
For more information, see 'Asynchronous exception routing' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.
This field resets to an architecturally UNKNOWN value.
Non-secure bit.
NS | Meaning |
---|---|
0b0 |
Indicates that EL0 and EL1 are in Secure state. |
0b1 |
Indicates that Exception levels lower than EL3 are in Non-secure state, and so memory accesses from those Exception levels cannot access Secure memory. |
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return SCR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else SCR_EL3 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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