The DBGDTR2A characteristics are:
Allows external debuggers to access capability state within PE. Transfers lower 32 bits of the upper half of capabilities. It is a component of the Debug Communications Channel.
External register DBGDTR2A bits [31:0] are architecturally mapped to AArch64 System register CDBGDTR_EL0[95:64] .
DBGDTR2A is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
This register is present only when Morello is implemented. Otherwise, direct accesses to DBGDTR2A are RES0.
DBGDTR2A is a 32-bit register.
The DBGDTR2A bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DTR2A |
Data transfer register for bits 95:64 of capability tranfers.
On a Cold reset, this field resets to an UNKNOWN value.
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
Component | Offset | Instance |
---|---|---|
Debug | 0x040 | DBGDTR2A |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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