RMR_EL3, Reset Management Register (EL3)

The RMR_EL3 characteristics are:

Purpose

If EL3 is the implemented and this register is implemented:

Configuration

AArch64 System register RMR_EL3 bits [31:0] are architecturally mapped to AArch32 System register RMR[31:0] when HaveEL(EL3).

When EL3 is implemented:

Otherwise, direct accesses to RMR_EL3 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

RMR_EL3 is a 64-bit register.

Field descriptions

The RMR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0RRAA64
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

RR, bit [1]

Reset Request. Setting this bit to 1 requests a Warm reset.

This field resets to 0.

AA64, bit [0]

When EL3 can use AArch32, determines which Execution state the PE boots into after a Warm reset:

AA64Meaning
0b0

AArch32.

0b1

AArch64.

On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.

If EL3 cannot use AArch32 this bit is RAO/WI.

When implemented as a RW field, this field resets to 1 on a Cold reset.

Accessing the RMR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, RMR_EL3

op0op1CRnCRmop2
0b110b1100b11000b00000b010

if PSTATE.EL == EL3 && IsHighestEL(EL3) then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return RMR_EL3; else UNDEFINED;

MSR RMR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b11000b00000b010

if PSTATE.EL == EL3 && IsHighestEL(EL3) then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else RMR_EL3 = X[t]; else UNDEFINED;




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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