CHCR_EL2, Capability Hypervisor Configuration Register

The CHCR_EL2 characteristics are:

Purpose

Provides control over privileged access to capabilities

Configuration

This register is present only when Morello is implemented. Otherwise, direct accesses to CHCR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

The bits in this register behave as if they are 0 for all purposes other than direct reads of the register if EL2 is not enabled in the current Security state.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CHCR_EL2 is a 64-bit register.

Field descriptions

The CHCR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0SETTAG
313029282726252423222120191817161514131211109876543210

Bits [63:1]

Reserved, RES0.

SETTAG, bit [0]

Access to privileged capability creating instructions, SCTAG and STCT.

SETTAGMeaning
0b0

No effect.

0b1

Privileged capability creating instructions clear the tag if executed at EL1.

This field resets to an architecturally UNKNOWN value.

Accessing the CHCR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, CHCR_EL2

op0op1CRnCRmop2
0b110b1000b00010b00100b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CHCR_EL2; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CHCR_EL2;

MSR CHCR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00010b00100b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CHCR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CHCR_EL2 = X[t];




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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