Below are indexes for registers with the following main functional groups:
Exec state | Name | Description |
---|---|---|
AArch64 | CCSIDR_EL1 | Current Cache Size ID Register |
AArch64 | CLIDR_EL1 | Cache Level ID Register |
AArch64 | CSSELR_EL1 | Cache Size Selection Register |
AArch64 | CTR_EL0 | Cache Type Register |
AArch64 | DCZID_EL0 | Data Cache Zero ID register |
AArch64 | ID_AA64AFR0_EL1 | AArch64 Auxiliary Feature Register 0 |
AArch64 | ID_AA64AFR1_EL1 | AArch64 Auxiliary Feature Register 1 |
AArch64 | ID_AA64DFR0_EL1 | AArch64 Debug Feature Register 0 |
AArch64 | ID_AA64DFR1_EL1 | AArch64 Debug Feature Register 1 |
AArch64 | ID_AA64ISAR0_EL1 | AArch64 Instruction Set Attribute Register 0 |
AArch64 | ID_AA64ISAR1_EL1 | AArch64 Instruction Set Attribute Register 1 |
AArch64 | ID_AA64MMFR0_EL1 | AArch64 Memory Model Feature Register 0 |
AArch64 | ID_AA64MMFR1_EL1 | AArch64 Memory Model Feature Register 1 |
AArch64 | ID_AA64MMFR2_EL1 | AArch64 Memory Model Feature Register 2 |
AArch64 | ID_AA64PFR0_EL1 | AArch64 Processor Feature Register 0 |
AArch64 | ID_AA64PFR1_EL1 | AArch64 Processor Feature Register 1 |
AArch64 | ID_AFR0_EL1 | AArch32 Auxiliary Feature Register 0 |
AArch64 | ID_DFR0_EL1 | AArch32 Debug Feature Register 0 |
AArch64 | ID_ISAR0_EL1 | AArch32 Instruction Set Attribute Register 0 |
AArch64 | ID_ISAR1_EL1 | AArch32 Instruction Set Attribute Register 1 |
AArch64 | ID_ISAR2_EL1 | AArch32 Instruction Set Attribute Register 2 |
AArch64 | ID_ISAR3_EL1 | AArch32 Instruction Set Attribute Register 3 |
AArch64 | ID_ISAR4_EL1 | AArch32 Instruction Set Attribute Register 4 |
AArch64 | ID_ISAR5_EL1 | AArch32 Instruction Set Attribute Register 5 |
AArch64 | ID_ISAR6_EL1 | AArch32 Instruction Set Attribute Register 6 |
AArch64 | ID_MMFR0_EL1 | AArch32 Memory Model Feature Register 0 |
AArch64 | ID_MMFR1_EL1 | AArch32 Memory Model Feature Register 1 |
AArch64 | ID_MMFR2_EL1 | AArch32 Memory Model Feature Register 2 |
AArch64 | ID_MMFR3_EL1 | AArch32 Memory Model Feature Register 3 |
AArch64 | ID_MMFR4_EL1 | AArch32 Memory Model Feature Register 4 |
AArch64 | ID_MMFR5_EL1 | AArch32 Memory Model Feature Register 5 |
AArch64 | ID_PFR0_EL1 | AArch32 Processor Feature Register 0 |
AArch64 | ID_PFR1_EL1 | AArch32 Processor Feature Register 1 |
AArch64 | ID_PFR2_EL1 | AArch32 Processor Feature Register 2 |
AArch64 | MIDR_EL1 | Main ID Register |
AArch64 | MPIDR_EL1 | Multiprocessor Affinity Register |
AArch64 | REVIDR_EL1 | Revision ID Register |
External | EDAA32PFR | External Debug AArch32 Processor Feature Register |
External | EDDFR | External Debug Feature Register |
External | EDPFR | External Debug Processor Feature Register |
External | MIDR_EL1 | Main ID Register |
Exec state | Name | Description |
---|---|---|
AArch64 | AMAIR_EL1 | Auxiliary Memory Attribute Indirection Register (EL1) |
AArch64 | AMAIR_EL2 | Auxiliary Memory Attribute Indirection Register (EL2) |
AArch64 | AMAIR_EL3 | Auxiliary Memory Attribute Indirection Register (EL3) |
AArch64 | CONTEXTIDR_EL1 | Context ID Register (EL1) |
AArch64 | CONTEXTIDR_EL2 | Context ID Register (EL2) |
AArch64 | DACR32_EL2 | Domain Access Control Register |
AArch64 | LORC_EL1 | LORegion Control (EL1) |
AArch64 | LOREA_EL1 | LORegion End Address (EL1) |
AArch64 | LORID_EL1 | LORegionID (EL1) |
AArch64 | LORN_EL1 | LORegion Number (EL1) |
AArch64 | LORSA_EL1 | LORegion Start Address (EL1) |
AArch64 | MAIR_EL1 | Memory Attribute Indirection Register (EL1) |
AArch64 | MAIR_EL2 | Memory Attribute Indirection Register (EL2) |
AArch64 | MAIR_EL3 | Memory Attribute Indirection Register (EL3) |
AArch64 | TCR_EL1 | Translation Control Register (EL1) |
AArch64 | TCR_EL2 | Translation Control Register (EL2) |
AArch64 | TCR_EL3 | Translation Control Register (EL3) |
AArch64 | TTBR0_EL1 | Translation Table Base Register 0 (EL1) |
AArch64 | TTBR0_EL2 | Translation Table Base Register 0 (EL2) |
AArch64 | TTBR0_EL3 | Translation Table Base Register 0 (EL3) |
AArch64 | TTBR1_EL1 | Translation Table Base Register 1 (EL1) |
AArch64 | TTBR1_EL2 | Translation Table Base Register 1 (EL2) |
AArch64 | VTCR_EL2 | Virtualization Translation Control Register |
AArch64 | VTTBR_EL2 | Virtualization Translation Table Base Register |
Exec state | Name | Description |
---|---|---|
AArch64 | CPACR_EL1 | Architectural Feature Access Control Register |
AArch64 | SCTLR_EL1 | System Control Register (EL1) |
AArch64 | SCTLR_EL3 | System Control Register (EL3) |
Exec state | Name | Description |
---|---|---|
AArch64 | AFSR0_EL1 | Auxiliary Fault Status Register 0 (EL1) |
AArch64 | AFSR0_EL2 | Auxiliary Fault Status Register 0 (EL2) |
AArch64 | AFSR0_EL3 | Auxiliary Fault Status Register 0 (EL3) |
AArch64 | AFSR1_EL1 | Auxiliary Fault Status Register 1 (EL1) |
AArch64 | AFSR1_EL2 | Auxiliary Fault Status Register 1 (EL2) |
AArch64 | AFSR1_EL3 | Auxiliary Fault Status Register 1 (EL3) |
AArch64 | ESR_EL1 | Exception Syndrome Register (EL1) |
AArch64 | ESR_EL2 | Exception Syndrome Register (EL2) |
AArch64 | ESR_EL3 | Exception Syndrome Register (EL3) |
AArch64 | FAR_EL1 | Fault Address Register (EL1) |
AArch64 | FAR_EL2 | Fault Address Register (EL2) |
AArch64 | FAR_EL3 | Fault Address Register (EL3) |
AArch64 | HPFAR_EL2 | Hypervisor IPA Fault Address Register |
AArch64 | IFSR32_EL2 | Instruction Fault Status Register (EL2) |
AArch64 | ISR_EL1 | Interrupt Status Register |
AArch64 | VBAR_EL1 | Vector Base Address Register (EL1) |
AArch64 | VBAR_EL2 | Vector Base Address Register (EL2) |
AArch64 | VBAR_EL3 | Vector Base Address Register (EL3) |
Exec state | Name | Description |
---|---|---|
AArch64 | DDC_EL0 | Default Data Capability (EL0) |
AArch64 | DDC_EL1 | Default Data Capability (EL1) |
AArch64 | DDC_EL2 | Default Data Capability (EL2) |
AArch64 | DDC_EL3 | Default Data Capability (EL3) |
AArch64 | ELR_EL1 | Exception Link Register (EL1) |
AArch64 | ELR_EL2 | Exception Link Register (EL2) |
AArch64 | ELR_EL3 | Exception Link Register (EL3) |
AArch64 | RDDC_EL0 | Restricted Default Data Capability |
AArch64 | RSP_EL0 | Restricted Stack Pointer |
AArch64 | SPSR_EL1 | Saved Program Status Register (EL1) |
AArch64 | SPSR_EL2 | Saved Program Status Register (EL2) |
AArch64 | SPSR_EL3 | Saved Program Status Register (EL3) |
AArch64 | SPSR_abt | Saved Program Status Register (Abort mode) |
AArch64 | SPSR_fiq | Saved Program Status Register (FIQ mode) |
AArch64 | SPSR_irq | Saved Program Status Register (IRQ mode) |
AArch64 | SPSR_und | Saved Program Status Register (Undefined mode) |
AArch64 | SP_EL0 | Stack Pointer (EL0) |
AArch64 | SP_EL1 | Stack Pointer (EL1) |
AArch64 | SP_EL2 | Stack Pointer (EL2) |
AArch64 | SP_EL3 | Stack Pointer (EL3) |
Exec state | Name | Description |
---|---|---|
AArch64 | CurrentEL | Current Exception Level |
AArch64 | DAIF | Interrupt Mask Bits |
AArch64 | NZCV | Condition Flags |
AArch64 | PAN | Privileged Access Never |
AArch64 | SPSel | Stack Pointer Select |
AArch64 | SSBS | Speculative Store Bypass Safe |
AArch64 | UAO | User Access Override |
Exec state | Name | Description |
---|---|---|
AArch64 | DC CISW | Data or unified Cache line Clean and Invalidate by Set/Way |
AArch64 | DC CIVAC | Data or unified Cache line Clean and Invalidate by VA to PoC |
AArch64 | DC CSW | Data or unified Cache line Clean by Set/Way |
AArch64 | DC CVAC | Data or unified Cache line Clean by VA to PoC |
AArch64 | DC CVADP | Data or unified Cache line Clean by VA to PoDP |
AArch64 | DC CVAP | Data or unified Cache line Clean by VA to PoP |
AArch64 | DC CVAU | Data or unified Cache line Clean by VA to PoU |
AArch64 | DC ISW | Data or unified Cache line Invalidate by Set/Way |
AArch64 | DC IVAC | Data or unified Cache line Invalidate by VA to PoC |
AArch64 | DC ZVA | Data Cache Zero by VA |
AArch64 | IC IALLU | Instruction Cache Invalidate All to PoU |
AArch64 | IC IALLUIS | Instruction Cache Invalidate All to PoU, Inner Shareable |
AArch64 | IC IVAU | Instruction Cache line Invalidate by VA to PoU |
Exec state | Name | Description |
---|---|---|
AArch64 | AT S12E0R | Address Translate Stages 1 and 2 EL0 Read |
AArch64 | AT S12E0W | Address Translate Stages 1 and 2 EL0 Write |
AArch64 | AT S12E1R | Address Translate Stages 1 and 2 EL1 Read |
AArch64 | AT S12E1W | Address Translate Stages 1 and 2 EL1 Write |
AArch64 | AT S1E0R | Address Translate Stage 1 EL0 Read |
AArch64 | AT S1E0W | Address Translate Stage 1 EL0 Write |
AArch64 | AT S1E1R | Address Translate Stage 1 EL1 Read |
AArch64 | AT S1E1RP | Address Translate Stage 1 EL1 Read PAN |
AArch64 | AT S1E1W | Address Translate Stage 1 EL1 Write |
AArch64 | AT S1E1WP | Address Translate Stage 1 EL1 Write PAN |
AArch64 | AT S1E2R | Address Translate Stage 1 EL2 Read |
AArch64 | AT S1E2W | Address Translate Stage 1 EL2 Write |
AArch64 | AT S1E3R | Address Translate Stage 1 EL3 Read |
AArch64 | AT S1E3W | Address Translate Stage 1 EL3 Write |
AArch64 | PAR_EL1 | Physical Address Register |
Exec state | Name | Description |
---|---|---|
AArch64 | TLBI ALLE1 | TLB Invalidate All, EL1 |
AArch64 | TLBI ALLE1IS | TLB Invalidate All, EL1, Inner Shareable |
AArch64 | TLBI ALLE2 | TLB Invalidate All, EL2 |
AArch64 | TLBI ALLE2IS | TLB Invalidate All, EL2, Inner Shareable |
AArch64 | TLBI ALLE3 | TLB Invalidate All, EL3 |
AArch64 | TLBI ALLE3IS | TLB Invalidate All, EL3, Inner Shareable |
AArch64 | TLBI ASIDE1 | TLB Invalidate by ASID, EL1 |
AArch64 | TLBI ASIDE1IS | TLB Invalidate by ASID, EL1, Inner Shareable |
AArch64 | TLBI IPAS2E1 | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1 |
AArch64 | TLBI IPAS2E1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable |
AArch64 | TLBI IPAS2LE1 | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1 |
AArch64 | TLBI IPAS2LE1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable |
AArch64 | TLBI VAAE1 | TLB Invalidate by VA, All ASID, EL1 |
AArch64 | TLBI VAAE1IS | TLB Invalidate by VA, All ASID, EL1, Inner Shareable |
AArch64 | TLBI VAALE1 | TLB Invalidate by VA, All ASID, Last level, EL1 |
AArch64 | TLBI VAALE1IS | TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable |
AArch64 | TLBI VAE1 | TLB Invalidate by VA, EL1 |
AArch64 | TLBI VAE1IS | TLB Invalidate by VA, EL1, Inner Shareable |
AArch64 | TLBI VAE2 | TLB Invalidate by VA, EL2 |
AArch64 | TLBI VAE2IS | TLB Invalidate by VA, EL2, Inner Shareable |
AArch64 | TLBI VAE3 | TLB Invalidate by VA, EL3 |
AArch64 | TLBI VAE3IS | TLB Invalidate by VA, EL3, Inner Shareable |
AArch64 | TLBI VALE1 | TLB Invalidate by VA, Last level, EL1 |
AArch64 | TLBI VALE1IS | TLB Invalidate by VA, Last level, EL1, Inner Shareable |
AArch64 | TLBI VALE2 | TLB Invalidate by VA, Last level, EL2 |
AArch64 | TLBI VALE2IS | TLB Invalidate by VA, Last level, EL2, Inner Shareable |
AArch64 | TLBI VALE3 | TLB Invalidate by VA, Last level, EL3 |
AArch64 | TLBI VALE3IS | TLB Invalidate by VA, Last level, EL3, Inner Shareable |
AArch64 | TLBI VMALLE1 | TLB Invalidate by VMID, All at stage 1, EL1 |
AArch64 | TLBI VMALLE1IS | TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable |
AArch64 | TLBI VMALLS12E1 | TLB Invalidate by VMID, All at Stage 1 and 2, EL1 |
AArch64 | TLBI VMALLS12E1IS | TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable |
Exec state | Name | Description |
---|---|---|
AArch64 | PMCCFILTR_EL0 | Performance Monitors Cycle Count Filter Register |
AArch64 | PMCCNTR_EL0 | Performance Monitors Cycle Count Register |
AArch64 | PMCEID0_EL0 | Performance Monitors Common Event Identification register 0 |
AArch64 | PMCEID1_EL0 | Performance Monitors Common Event Identification register 1 |
AArch64 | PMCNTENCLR_EL0 | Performance Monitors Count Enable Clear register |
AArch64 | PMCNTENSET_EL0 | Performance Monitors Count Enable Set register |
AArch64 | PMCR_EL0 | Performance Monitors Control Register |
AArch64 | PMEVCNTR<n>_EL0 | Performance Monitors Event Count Registers |
AArch64 | PMEVTYPER<n>_EL0 | Performance Monitors Event Type Registers |
AArch64 | PMINTENCLR_EL1 | Performance Monitors Interrupt Enable Clear register |
AArch64 | PMINTENSET_EL1 | Performance Monitors Interrupt Enable Set register |
AArch64 | PMOVSCLR_EL0 | Performance Monitors Overflow Flag Status Clear Register |
AArch64 | PMOVSSET_EL0 | Performance Monitors Overflow Flag Status Set register |
AArch64 | PMSELR_EL0 | Performance Monitors Event Counter Selection Register |
AArch64 | PMSWINC_EL0 | Performance Monitors Software Increment register |
AArch64 | PMUSERENR_EL0 | Performance Monitors User Enable Register |
AArch64 | PMXEVCNTR_EL0 | Performance Monitors Selected Event Count Register |
AArch64 | PMXEVTYPER_EL0 | Performance Monitors Selected Event Type Register |
External | PMAUTHSTATUS | Performance Monitors Authentication Status register |
External | PMCCFILTR_EL0 | Performance Monitors Cycle Counter Filter Register |
External | PMCCNTR_EL0 | Performance Monitors Cycle Counter |
External | PMCEID0 | Performance Monitors Common Event Identification register 0 |
External | PMCEID1 | Performance Monitors Common Event Identification register 1 |
External | PMCEID2 | Performance Monitors Common Event Identification register 2 |
External | PMCEID3 | Performance Monitors Common Event Identification register 3 |
External | PMCFGR | Performance Monitors Configuration Register |
External | PMCID1SR | CONTEXTIDR_EL1 Sample Register |
External | PMCID2SR | CONTEXTIDR_EL2 Sample Register |
External | PMCIDR0 | Performance Monitors Component Identification Register 0 |
External | PMCIDR1 | Performance Monitors Component Identification Register 1 |
External | PMCIDR2 | Performance Monitors Component Identification Register 2 |
External | PMCIDR3 | Performance Monitors Component Identification Register 3 |
External | PMCNTENCLR_EL0 | Performance Monitors Count Enable Clear register |
External | PMCNTENSET_EL0 | Performance Monitors Count Enable Set register |
External | PMCR_EL0 | Performance Monitors Control Register |
External | PMDEVAFF0 | Performance Monitors Device Affinity register 0 |
External | PMDEVAFF1 | Performance Monitors Device Affinity register 1 |
External | PMDEVARCH | Performance Monitors Device Architecture register |
External | PMDEVID | Performance Monitors Device ID register |
External | PMDEVTYPE | Performance Monitors Device Type register |
External | PMEVCNTR<n>_EL0 | Performance Monitors Event Count Registers |
External | PMEVTYPER<n>_EL0 | Performance Monitors Event Type Registers |
External | PMINTENCLR_EL1 | Performance Monitors Interrupt Enable Clear register |
External | PMINTENSET_EL1 | Performance Monitors Interrupt Enable Set register |
External | PMITCTRL | Performance Monitors Integration mode Control register |
External | PMLAR | Performance Monitors Lock Access Register |
External | PMLSR | Performance Monitors Lock Status Register |
External | PMOVSCLR_EL0 | Performance Monitors Overflow Flag Status Clear register |
External | PMOVSSET_EL0 | Performance Monitors Overflow Flag Status Set register |
External | PMPCSR | Program Counter Sample Register |
External | PMPIDR0 | Performance Monitors Peripheral Identification Register 0 |
External | PMPIDR1 | Performance Monitors Peripheral Identification Register 1 |
External | PMPIDR2 | Performance Monitors Peripheral Identification Register 2 |
External | PMPIDR3 | Performance Monitors Peripheral Identification Register 3 |
External | PMPIDR4 | Performance Monitors Peripheral Identification Register 4 |
External | PMSWINC_EL0 | Performance Monitors Software Increment register |
External | PMVIDSR | VMID Sample Register |
Exec state | Name | Description |
---|---|---|
AArch64 | RMR_EL1 | Reset Management Register (EL1) |
AArch64 | RMR_EL2 | Reset Management Register (EL2) |
AArch64 | RMR_EL3 | Reset Management Register (EL3) |
AArch64 | RVBAR_EL1 | Reset Vector Base Address Register (if EL2 and EL3 not implemented) |
AArch64 | RVBAR_EL2 | Reset Vector Base Address Register (if EL3 not implemented) |
AArch64 | RVBAR_EL3 | Reset Vector Base Address Register (if EL3 implemented) |
Exec state | Name | Description |
---|---|---|
AArch64 | CID_EL0 | Compartment ID Register |
AArch64 | RTPIDR_EL0 | Restricted Read/Write Software Thread ID Register |
AArch64 | SCXTNUM_EL0 | EL0 Read/Write Software Context Number |
AArch64 | SCXTNUM_EL1 | EL1 Read/Write Software Context Number |
AArch64 | SCXTNUM_EL2 | EL2 Read/Write Software Context Number |
AArch64 | SCXTNUM_EL3 | EL3 Read/Write Software Context Number |
AArch64 | TPIDRRO_EL0 | EL0 Read-Only Software Thread ID Register |
AArch64 | TPIDR_EL0 | EL0 Read/Write Software Thread ID Register |
AArch64 | TPIDR_EL1 | EL1 Software Thread ID Register |
AArch64 | TPIDR_EL2 | EL2 Software Thread ID Register |
AArch64 | TPIDR_EL3 | EL3 Software Thread ID Register |
Exec state | Name | Description |
---|---|---|
AArch64 | ACTLR_EL1 | Auxiliary Control Register (EL1) |
AArch64 | ACTLR_EL2 | Auxiliary Control Register (EL2) |
AArch64 | ACTLR_EL3 | Auxiliary Control Register (EL3) |
AArch64 | AFSR0_EL1 | Auxiliary Fault Status Register 0 (EL1) |
AArch64 | AFSR0_EL2 | Auxiliary Fault Status Register 0 (EL2) |
AArch64 | AFSR0_EL3 | Auxiliary Fault Status Register 0 (EL3) |
AArch64 | AFSR1_EL1 | Auxiliary Fault Status Register 1 (EL1) |
AArch64 | AFSR1_EL2 | Auxiliary Fault Status Register 1 (EL2) |
AArch64 | AFSR1_EL3 | Auxiliary Fault Status Register 1 (EL3) |
AArch64 | AIDR_EL1 | Auxiliary ID Register |
AArch64 | AMAIR_EL1 | Auxiliary Memory Attribute Indirection Register (EL1) |
AArch64 | AMAIR_EL2 | Auxiliary Memory Attribute Indirection Register (EL2) |
AArch64 | AMAIR_EL3 | Auxiliary Memory Attribute Indirection Register (EL3) |
AArch64 | HACR_EL2 | Hypervisor Auxiliary Control Register |
AArch64 | S1_<op1>_<Cn>_<Cm>_<op2> | IMPLEMENTATION DEFINED maintenance instructions |
AArch64 | S3_<op1>_<Cn>_<Cm>_<op2> | IMPLEMENTATION DEFINED registers |
Exec state | Name | Description |
---|---|---|
AArch64 | CNTFRQ_EL0 | Counter-timer Frequency register |
AArch64 | CNTHV_CTL_EL2 | Counter-timer Virtual Timer Control register (EL2) |
AArch64 | CNTHV_CVAL_EL2 | Counter-timer Virtual Timer CompareValue register (EL2) |
AArch64 | CNTHV_TVAL_EL2 | Counter-timer Virtual Timer TimerValue Register (EL2) |
AArch64 | CNTKCTL_EL1 | Counter-timer Kernel Control register |
AArch64 | CNTPCT_EL0 | Counter-timer Physical Count register |
AArch64 | CNTPS_CTL_EL1 | Counter-timer Physical Secure Timer Control register |
AArch64 | CNTPS_CVAL_EL1 | Counter-timer Physical Secure Timer CompareValue register |
AArch64 | CNTPS_TVAL_EL1 | Counter-timer Physical Secure Timer TimerValue register |
AArch64 | CNTP_CTL_EL0 | Counter-timer Physical Timer Control register |
AArch64 | CNTP_CVAL_EL0 | Counter-timer Physical Timer CompareValue register |
AArch64 | CNTP_TVAL_EL0 | Counter-timer Physical Timer TimerValue register |
AArch64 | CNTVCT_EL0 | Counter-timer Virtual Count register |
AArch64 | CNTV_CTL_EL0 | Counter-timer Virtual Timer Control register |
AArch64 | CNTV_CVAL_EL0 | Counter-timer Virtual Timer CompareValue register |
AArch64 | CNTV_TVAL_EL0 | Counter-timer Virtual Timer TimerValue register |
External | CNTACR<n> | Counter-timer Access Control Registers |
External | CNTCR | Counter Control Register |
External | CNTCV | Counter Count Value register |
External | CNTEL0ACR | Counter-timer EL0 Access Control Register |
External | CNTFID0 | Counter Frequency ID |
External | CNTFID<n> | Counter Frequency IDs, n > 0 |
External | CNTFRQ | Counter-timer Frequency |
External | CNTNSAR | Counter-timer Non-secure Access Register |
External | CNTPCT | Counter-timer Physical Count |
External | CNTP_CTL | Counter-timer Physical Timer Control |
External | CNTP_CVAL | Counter-timer Physical Timer CompareValue |
External | CNTP_TVAL | Counter-timer Physical Timer TimerValue |
External | CNTSR | Counter Status Register |
External | CNTTIDR | Counter-timer Timer ID Register |
External | CNTVCT | Counter-timer Virtual Count |
External | CNTVOFF | Counter-timer Virtual Offset |
External | CNTVOFF<n> | Counter-timer Virtual Offsets |
External | CNTV_CTL | Counter-timer Virtual Timer Control |
External | CNTV_CVAL | Counter-timer Virtual Timer CompareValue |
External | CNTV_TVAL | Counter-timer Virtual Timer TimerValue |
External | CounterID<n> | Counter ID registers |
Exec state | Name | Description |
---|---|---|
AArch64 | CDBGDTR_EL0 | Capability Debug Data Transfer Register, half-duplex |
AArch64 | CDLR_EL0 | Capability Debug Link Register |
AArch64 | DBGAUTHSTATUS_EL1 | Debug Authentication Status register |
AArch64 | DBGBCR<n>_EL1 | Debug Breakpoint Control Registers |
AArch64 | DBGBVR<n>_EL1 | Debug Breakpoint Value Registers |
AArch64 | DBGCLAIMCLR_EL1 | Debug CLAIM Tag Clear register |
AArch64 | DBGCLAIMSET_EL1 | Debug CLAIM Tag Set register |
AArch64 | DBGDTRRX_EL0 | Debug Data Transfer Register, Receive |
AArch64 | DBGDTRTX_EL0 | Debug Data Transfer Register, Transmit |
AArch64 | DBGDTR_EL0 | Debug Data Transfer Register, half-duplex |
AArch64 | DBGPRCR_EL1 | Debug Power Control Register |
AArch64 | DBGVCR32_EL2 | Debug Vector Catch Register |
AArch64 | DBGWCR<n>_EL1 | Debug Watchpoint Control Registers |
AArch64 | DBGWVR<n>_EL1 | Debug Watchpoint Value Registers |
AArch64 | DLR_EL0 | Debug Link Register |
AArch64 | DSPSR_EL0 | Debug Saved Program Status Register |
AArch64 | MDCCINT_EL1 | Monitor DCC Interrupt Enable Register |
AArch64 | MDCCSR_EL0 | Monitor DCC Status Register |
AArch64 | MDRAR_EL1 | Monitor Debug ROM Address Register |
AArch64 | MDSCR_EL1 | Monitor Debug System Control Register |
AArch64 | OSDLR_EL1 | OS Double Lock Register |
AArch64 | OSDTRRX_EL1 | OS Lock Data Transfer Register, Receive |
AArch64 | OSDTRTX_EL1 | OS Lock Data Transfer Register, Transmit |
AArch64 | OSECCR_EL1 | OS Lock Exception Catch Control Register |
AArch64 | OSLAR_EL1 | OS Lock Access Register |
AArch64 | OSLSR_EL1 | OS Lock Status Register |
External | DBGAUTHSTATUS_EL1 | Debug Authentication Status register |
External | DBGBCR<n>_EL1 | Debug Breakpoint Control Registers |
External | DBGBVR<n>_EL1 | Debug Breakpoint Value Registers |
External | DBGCLAIMCLR_EL1 | Debug CLAIM Tag Clear register |
External | DBGCLAIMSET_EL1 | Debug CLAIM Tag Set register |
External | DBGDTR2A | Debug Data Transfer Register 2A |
External | DBGDTR2B | Debug Data Transfer Register 2B |
External | DBGDTRRX_EL0 | Debug Data Transfer Register, Receive |
External | DBGDTRTX_EL0 | Debug Data Transfer Register, Transmit |
External | DBGWCR<n>_EL1 | Debug Watchpoint Control Registers |
External | DBGWVR<n>_EL1 | Debug Watchpoint Value Registers |
External | EDACR | External Debug Auxiliary Control Register |
External | EDCIDR0 | External Debug Component Identification Register 0 |
External | EDCIDR1 | External Debug Component Identification Register 1 |
External | EDCIDR2 | External Debug Component Identification Register 2 |
External | EDCIDR3 | External Debug Component Identification Register 3 |
External | EDCIDSR | External Debug Context ID Sample Register |
External | EDDEVAFF0 | External Debug Device Affinity register 0 |
External | EDDEVAFF1 | External Debug Device Affinity register 1 |
External | EDDEVARCH | External Debug Device Architecture register |
External | EDDEVID | External Debug Device ID register 0 |
External | EDDEVID1 | External Debug Device ID register 1 |
External | EDDEVID2 | External Debug Device ID register 2 |
External | EDDEVTYPE | External Debug Device Type register |
External | EDECCR | External Debug Exception Catch Control Register |
External | EDECR | External Debug Execution Control Register |
External | EDESR | External Debug Event Status Register |
External | EDITCTRL | External Debug Integration mode Control register |
External | EDITR | External Debug Instruction Transfer Register |
External | EDLAR | External Debug Lock Access Register |
External | EDLSR | External Debug Lock Status Register |
External | EDPCSR | External Debug Program Counter Sample Register |
External | EDPIDR0 | External Debug Peripheral Identification Register 0 |
External | EDPIDR1 | External Debug Peripheral Identification Register 1 |
External | EDPIDR2 | External Debug Peripheral Identification Register 2 |
External | EDPIDR3 | External Debug Peripheral Identification Register 3 |
External | EDPIDR4 | External Debug Peripheral Identification Register 4 |
External | EDPRCR | External Debug Power/Reset Control Register |
External | EDPRSR | External Debug Processor Status Register |
External | EDRCR | External Debug Reserve Control Register |
External | EDSCR | External Debug Status and Control Register |
External | EDSCR2 | External Debug Status and Control Register 2 |
External | EDVIDSR | External Debug Virtual Context Sample Register |
External | EDWAR | External Debug Watchpoint Address Register |
External | OSLAR_EL1 | OS Lock Access Register |
Exec state | Name | Description |
---|---|---|
External | ASICCTL | CTI External Multiplexer Control register |
External | CTIAPPCLEAR | CTI Application Trigger Clear register |
External | CTIAPPPULSE | CTI Application Pulse register |
External | CTIAPPSET | CTI Application Trigger Set register |
External | CTIAUTHSTATUS | CTI Authentication Status register |
External | CTICHINSTATUS | CTI Channel In Status register |
External | CTICHOUTSTATUS | CTI Channel Out Status register |
External | CTICIDR0 | CTI Component Identification Register 0 |
External | CTICIDR1 | CTI Component Identification Register 1 |
External | CTICIDR2 | CTI Component Identification Register 2 |
External | CTICIDR3 | CTI Component Identification Register 3 |
External | CTICLAIMCLR | CTI CLAIM Tag Clear register |
External | CTICLAIMSET | CTI CLAIM Tag Set register |
External | CTICONTROL | CTI Control register |
External | CTIDEVAFF0 | CTI Device Affinity register 0 |
External | CTIDEVAFF1 | CTI Device Affinity register 1 |
External | CTIDEVARCH | CTI Device Architecture register |
External | CTIDEVID | CTI Device ID register 0 |
External | CTIDEVID1 | CTI Device ID register 1 |
External | CTIDEVID2 | CTI Device ID register 2 |
External | CTIDEVTYPE | CTI Device Type register |
External | CTIGATE | CTI Channel Gate Enable register |
External | CTIINEN<n> | CTI Input Trigger to Output Channel Enable registers |
External | CTIINTACK | CTI Output Trigger Acknowledge register |
External | CTIITCTRL | CTI Integration mode Control register |
External | CTILAR | CTI Lock Access Register |
External | CTILSR | CTI Lock Status Register |
External | CTIOUTEN<n> | CTI Input Channel to Output Trigger Enable registers |
External | CTIPIDR0 | CTI Peripheral Identification Register 0 |
External | CTIPIDR1 | CTI Peripheral Identification Register 1 |
External | CTIPIDR2 | CTI Peripheral Identification Register 2 |
External | CTIPIDR3 | CTI Peripheral Identification Register 3 |
External | CTIPIDR4 | CTI Peripheral Identification Register 4 |
External | CTITRIGINSTATUS | CTI Trigger In Status register |
External | CTITRIGOUTSTATUS | CTI Trigger Out Status register |
Exec state | Name | Description |
---|---|---|
AArch64 | ACTLR_EL2 | Auxiliary Control Register (EL2) |
AArch64 | AFSR0_EL2 | Auxiliary Fault Status Register 0 (EL2) |
AArch64 | AFSR1_EL2 | Auxiliary Fault Status Register 1 (EL2) |
AArch64 | AMAIR_EL2 | Auxiliary Memory Attribute Indirection Register (EL2) |
AArch64 | CCTLR_EL2 | Capability Control Register (EL2) |
AArch64 | CHCR_EL2 | Capability Hypervisor Configuration Register |
AArch64 | CNTHCTL_EL2 | Counter-timer Hypervisor Control register |
AArch64 | CNTHP_CTL_EL2 | Counter-timer Hypervisor Physical Timer Control register |
AArch64 | CNTHP_CVAL_EL2 | Counter-timer Physical Timer CompareValue register (EL2) |
AArch64 | CNTHP_TVAL_EL2 | Counter-timer Physical Timer TimerValue register (EL2) |
AArch64 | CNTVOFF_EL2 | Counter-timer Virtual Offset register |
AArch64 | CPTR_EL2 | Architectural Feature Trap Register (EL2) |
AArch64 | ESR_EL2 | Exception Syndrome Register (EL2) |
AArch64 | FAR_EL2 | Fault Address Register (EL2) |
AArch64 | HACR_EL2 | Hypervisor Auxiliary Control Register |
AArch64 | HCR_EL2 | Hypervisor Configuration Register |
AArch64 | HPFAR_EL2 | Hypervisor IPA Fault Address Register |
AArch64 | HSTR_EL2 | Hypervisor System Trap Register |
AArch64 | ICC_SRE_EL2 | Interrupt Controller System Register Enable register (EL2) |
AArch64 | ICH_AP0R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 0 Registers |
AArch64 | ICH_AP1R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 1 Registers |
AArch64 | ICH_EISR_EL2 | Interrupt Controller End of Interrupt Status Register |
AArch64 | ICH_ELRSR_EL2 | Interrupt Controller Empty List Register Status Register |
AArch64 | ICH_HCR_EL2 | Interrupt Controller Hyp Control Register |
AArch64 | ICH_LR<n>_EL2 | Interrupt Controller List Registers |
AArch64 | ICH_MISR_EL2 | Interrupt Controller Maintenance Interrupt State Register |
AArch64 | ICH_VMCR_EL2 | Interrupt Controller Virtual Machine Control Register |
AArch64 | ICH_VTR_EL2 | Interrupt Controller VGIC Type Register |
AArch64 | MAIR_EL2 | Memory Attribute Indirection Register (EL2) |
AArch64 | MDCR_EL2 | Monitor Debug Configuration Register (EL2) |
AArch64 | RMR_EL2 | Reset Management Register (EL2) |
AArch64 | SCTLR_EL2 | System Control Register (EL2) |
AArch64 | TCR_EL2 | Translation Control Register (EL2) |
AArch64 | TLBI IPAS2E1 | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1 |
AArch64 | TLBI IPAS2E1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable |
AArch64 | TLBI IPAS2LE1 | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1 |
AArch64 | TLBI IPAS2LE1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable |
AArch64 | TPIDR_EL2 | EL2 Software Thread ID Register |
AArch64 | TTBR0_EL2 | Translation Table Base Register 0 (EL2) |
AArch64 | TTBR1_EL2 | Translation Table Base Register 1 (EL2) |
AArch64 | VBAR_EL2 | Vector Base Address Register (EL2) |
AArch64 | VMPIDR_EL2 | Virtualization Multiprocessor ID Register |
AArch64 | VPIDR_EL2 | Virtualization Processor ID Register |
AArch64 | VTCR_EL2 | Virtualization Translation Control Register |
AArch64 | VTTBR_EL2 | Virtualization Translation Table Base Register |
Exec state | Name | Description |
---|---|---|
AArch64 | ACTLR_EL3 | Auxiliary Control Register (EL3) |
AArch64 | AFSR0_EL3 | Auxiliary Fault Status Register 0 (EL3) |
AArch64 | AFSR1_EL3 | Auxiliary Fault Status Register 1 (EL3) |
AArch64 | AMAIR_EL3 | Auxiliary Memory Attribute Indirection Register (EL3) |
AArch64 | CHCR_EL2 | Capability Hypervisor Configuration Register |
AArch64 | CPTR_EL3 | Architectural Feature Trap Register (EL3) |
AArch64 | CSCR_EL3 | Capability Secure Configuration Register |
AArch64 | ICC_CTLR_EL3 | Interrupt Controller Control Register (EL3) |
AArch64 | ICC_SRE_EL3 | Interrupt Controller System Register Enable register (EL3) |
AArch64 | MDCR_EL3 | Monitor Debug Configuration Register (EL3) |
AArch64 | SCR_EL3 | Secure Configuration Register |
AArch64 | SDER32_EL3 | AArch32 Secure Debug Enable Register |
AArch64 | VBAR_EL3 | Vector Base Address Register (EL3) |
Exec state | Name | Description |
---|---|---|
AArch64 | FPCR | Floating-point Control Register |
AArch64 | FPEXC32_EL2 | Floating-Point Exception Control register |
AArch64 | FPSR | Floating-point Status Register |
AArch64 | MVFR0_EL1 | AArch32 Media and VFP Feature Register 0 |
AArch64 | MVFR1_EL1 | AArch32 Media and VFP Feature Register 1 |
AArch64 | MVFR2_EL1 | AArch32 Media and VFP Feature Register 2 |
Exec state | Name | Description |
---|---|---|
AArch64 | ICC_AP0R<n>_EL1 | Interrupt Controller Active Priorities Group 0 Registers |
AArch64 | ICC_AP1R<n>_EL1 | Interrupt Controller Active Priorities Group 1 Registers |
AArch64 | ICC_ASGI1R_EL1 | Interrupt Controller Alias Software Generated Interrupt Group 1 Register |
AArch64 | ICC_BPR0_EL1 | Interrupt Controller Binary Point Register 0 |
AArch64 | ICC_BPR1_EL1 | Interrupt Controller Binary Point Register 1 |
AArch64 | ICC_CTLR_EL1 | Interrupt Controller Control Register (EL1) |
AArch64 | ICC_CTLR_EL3 | Interrupt Controller Control Register (EL3) |
AArch64 | ICC_DIR_EL1 | Interrupt Controller Deactivate Interrupt Register |
AArch64 | ICC_EOIR0_EL1 | Interrupt Controller End Of Interrupt Register 0 |
AArch64 | ICC_EOIR1_EL1 | Interrupt Controller End Of Interrupt Register 1 |
AArch64 | ICC_HPPIR0_EL1 | Interrupt Controller Highest Priority Pending Interrupt Register 0 |
AArch64 | ICC_HPPIR1_EL1 | Interrupt Controller Highest Priority Pending Interrupt Register 1 |
AArch64 | ICC_IAR0_EL1 | Interrupt Controller Interrupt Acknowledge Register 0 |
AArch64 | ICC_IAR1_EL1 | Interrupt Controller Interrupt Acknowledge Register 1 |
AArch64 | ICC_IGRPEN0_EL1 | Interrupt Controller Interrupt Group 0 Enable register |
AArch64 | ICC_IGRPEN1_EL1 | Interrupt Controller Interrupt Group 1 Enable register |
AArch64 | ICC_IGRPEN1_EL3 | Interrupt Controller Interrupt Group 1 Enable register (EL3) |
AArch64 | ICC_PMR_EL1 | Interrupt Controller Interrupt Priority Mask Register |
AArch64 | ICC_RPR_EL1 | Interrupt Controller Running Priority Register |
AArch64 | ICC_SGI0R_EL1 | Interrupt Controller Software Generated Interrupt Group 0 Register |
AArch64 | ICC_SGI1R_EL1 | Interrupt Controller Software Generated Interrupt Group 1 Register |
AArch64 | ICC_SRE_EL1 | Interrupt Controller System Register Enable register (EL1) |
AArch64 | ICC_SRE_EL2 | Interrupt Controller System Register Enable register (EL2) |
AArch64 | ICC_SRE_EL3 | Interrupt Controller System Register Enable register (EL3) |
AArch64 | ICH_AP0R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 0 Registers |
AArch64 | ICH_AP1R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 1 Registers |
AArch64 | ICH_EISR_EL2 | Interrupt Controller End of Interrupt Status Register |
AArch64 | ICH_ELRSR_EL2 | Interrupt Controller Empty List Register Status Register |
AArch64 | ICH_HCR_EL2 | Interrupt Controller Hyp Control Register |
AArch64 | ICH_LR<n>_EL2 | Interrupt Controller List Registers |
AArch64 | ICH_MISR_EL2 | Interrupt Controller Maintenance Interrupt State Register |
AArch64 | ICH_VMCR_EL2 | Interrupt Controller Virtual Machine Control Register |
AArch64 | ICH_VTR_EL2 | Interrupt Controller VGIC Type Register |
AArch64 | ICV_AP0R<n>_EL1 | Interrupt Controller Virtual Active Priorities Group 0 Registers |
AArch64 | ICV_AP1R<n>_EL1 | Interrupt Controller Virtual Active Priorities Group 1 Registers |
AArch64 | ICV_BPR0_EL1 | Interrupt Controller Virtual Binary Point Register 0 |
AArch64 | ICV_BPR1_EL1 | Interrupt Controller Virtual Binary Point Register 1 |
AArch64 | ICV_CTLR_EL1 | Interrupt Controller Virtual Control Register |
AArch64 | ICV_DIR_EL1 | Interrupt Controller Deactivate Virtual Interrupt Register |
AArch64 | ICV_EOIR0_EL1 | Interrupt Controller Virtual End Of Interrupt Register 0 |
AArch64 | ICV_EOIR1_EL1 | Interrupt Controller Virtual End Of Interrupt Register 1 |
AArch64 | ICV_HPPIR0_EL1 | Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0 |
AArch64 | ICV_HPPIR1_EL1 | Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1 |
AArch64 | ICV_IAR0_EL1 | Interrupt Controller Virtual Interrupt Acknowledge Register 0 |
AArch64 | ICV_IAR1_EL1 | Interrupt Controller Virtual Interrupt Acknowledge Register 1 |
AArch64 | ICV_IGRPEN0_EL1 | Interrupt Controller Virtual Interrupt Group 0 Enable register |
AArch64 | ICV_IGRPEN1_EL1 | Interrupt Controller Virtual Interrupt Group 1 Enable register |
AArch64 | ICV_PMR_EL1 | Interrupt Controller Virtual Interrupt Priority Mask Register |
AArch64 | ICV_RPR_EL1 | Interrupt Controller Virtual Running Priority Register |
Exec state | Name | Description |
---|---|---|
External | GICD_CLRSPI_NSR | Clear Non-secure SPI Pending Register |
External | GICD_CLRSPI_SR | Clear Secure SPI Pending Register |
External | GICD_CPENDSGIR<n> | SGI Clear-Pending Registers |
External | GICD_CTLR | Distributor Control Register |
External | GICD_ICACTIVER<n> | Interrupt Clear-Active Registers |
External | GICD_ICACTIVER<n>E | Interrupt Clear-Active Registers (extended SPI range) |
External | GICD_ICENABLER<n> | Interrupt Clear-Enable Registers |
External | GICD_ICENABLER<n>E | Interrupt Clear-Enable Registers |
External | GICD_ICFGR<n> | Interrupt Configuration Registers |
External | GICD_ICFGR<n>E | Interrupt Configuration Registers (Extended SPI Range) |
External | GICD_ICPENDR<n> | Interrupt Clear-Pending Registers |
External | GICD_ICPENDR<n>E | Interrupt Clear-Pending Registers (extended SPI range) |
External | GICD_IGROUPR<n> | Interrupt Group Registers |
External | GICD_IGROUPR<n>E | Interrupt Group Registers (extended SPI range) |
External | GICD_IGRPMODR<n> | Interrupt Group Modifier Registers |
External | GICD_IGRPMODR<n>E | Interrupt Group Modifier Registers (extended SPI range) |
External | GICD_IIDR | Distributor Implementer Identification Register |
External | GICD_IPRIORITYR<n> | Interrupt Priority Registers |
External | GICD_IPRIORITYR<n>E | Holds the priority of the corresponding interrupt for each extended SPI supported by the GIC. |
External | GICD_IROUTER<n> | Interrupt Routing Registers |
External | GICD_IROUTER<n>E | Interrupt Routing Registers (Extended SPI Range) |
External | GICD_ISACTIVER<n> | Interrupt Set-Active Registers |
External | GICD_ISACTIVER<n>E | Interrupt Set-Active Registers (extended SPI range) |
External | GICD_ISENABLER<n> | Interrupt Set-Enable Registers |
External | GICD_ISENABLER<n>E | Interrupt Set-Enable Registers |
External | GICD_ISPENDR<n> | Interrupt Set-Pending Registers |
External | GICD_ISPENDR<n>E | Interrupt Set-Pending Registers (extended SPI range) |
External | GICD_ITARGETSR<n> | Interrupt Processor Targets Registers |
External | GICD_NSACR<n> | Non-secure Access Control Registers |
External | GICD_NSACR<n>E | Non-secure Access Control Registers |
External | GICD_SETSPI_NSR | Set Non-secure SPI Pending Register |
External | GICD_SETSPI_SR | Set Secure SPI Pending Register |
External | GICD_SGIR | Software Generated Interrupt Register |
External | GICD_SPENDSGIR<n> | SGI Set-Pending Registers |
External | GICD_STATUSR | Error Reporting Status Register |
External | GICD_TYPER | Interrupt Controller Type Register |
Exec state | Name | Description |
---|---|---|
External | GICR_CLRLPIR | Clear LPI Pending Register |
External | GICR_CTLR | Redistributor Control Register |
External | GICR_ICACTIVER0 | Interrupt Clear-Active Register 0 |
External | GICR_ICACTIVER<n>E | Interrupt Clear-Active Registers |
External | GICR_ICENABLER0 | Interrupt Clear-Enable Register 0 |
External | GICR_ICENABLER<n>E | Interrupt Clear-Enable Registers |
External | GICR_ICFGR0 | Interrupt Configuration Register 0 |
External | GICR_ICFGR1 | Interrupt Configuration Register 1 |
External | GICR_ICFGR<n>E | Interrupt configuration registers |
External | GICR_ICPENDR0 | Interrupt Clear-Pending Register 0 |
External | GICR_ICPENDR<n>E | Interrupt Clear-Pending Registers |
External | GICR_IGROUPR0 | Interrupt Group Register 0 |
External | GICR_IGROUPR<n>E | Interrupt Group Registers |
External | GICR_IGRPMODR0 | Interrupt Group Modifier Register 0 |
External | GICR_IGRPMODR<n>E | Interrupt Group Modifier Registers |
External | GICR_IIDR | Redistributor Implementer Identification Register |
External | GICR_INVALLR | Redistributor Invalidate All Register |
External | GICR_INVLPIR | Redistributor Invalidate LPI Register |
External | GICR_IPRIORITYR<n> | Interrupt Priority Registers |
External | GICR_IPRIORITYR<n>E | Interrupt Priority Registers (extended PPI range) |
External | GICR_ISACTIVER0 | Interrupt Set-Active Register 0 |
External | GICR_ISACTIVER<n>E | Interrupt Set-Active Registers |
External | GICR_ISENABLER0 | Interrupt Set-Enable Register 0 |
External | GICR_ISENABLER<n>E | Interrupt Set-Enable Registers |
External | GICR_ISPENDR0 | Interrupt Set-Pending Register 0 |
External | GICR_ISPENDR<n>E | Interrupt Set-Pending Registers |
External | GICR_MPAMIDR | Report maximum PARTID and PMG Register |
External | GICR_NSACR | Non-secure Access Control Register |
External | GICR_PARTIDR | Set PARTID and PMG Register |
External | GICR_PENDBASER | Redistributor LPI Pending Table Base Address Register |
External | GICR_PROPBASER | Redistributor Properties Base Address Register |
External | GICR_SETLPIR | Set LPI Pending Register |
External | GICR_STATUSR | Error Reporting Status Register |
External | GICR_SYNCR | Redistributor Synchronize Register |
External | GICR_TYPER | Redistributor Type Register |
External | GICR_VPENDBASER | Virtual Redistributor LPI Pending Table Base Address Register |
External | GICR_VPROPBASER | Virtual Redistributor Properties Base Address Register |
External | GICR_WAKER | Redistributor Wake Register |
Exec state | Name | Description |
---|---|---|
External | GICC_ABPR | CPU Interface Aliased Binary Point Register |
External | GICC_AEOIR | CPU Interface Aliased End Of Interrupt Register |
External | GICC_AHPPIR | CPU Interface Aliased Highest Priority Pending Interrupt Register |
External | GICC_AIAR | CPU Interface Aliased Interrupt Acknowledge Register |
External | GICC_APR<n> | CPU Interface Active Priorities Registers |
External | GICC_BPR | CPU Interface Binary Point Register |
External | GICC_CTLR | CPU Interface Control Register |
External | GICC_DIR | CPU Interface Deactivate Interrupt Register |
External | GICC_EOIR | CPU Interface End Of Interrupt Register |
External | GICC_HPPIR | CPU Interface Highest Priority Pending Interrupt Register |
External | GICC_IAR | CPU Interface Interrupt Acknowledge Register |
External | GICC_IIDR | CPU Interface Identification Register |
External | GICC_NSAPR<n> | CPU Interface Non-secure Active Priorities Registers |
External | GICC_PMR | CPU Interface Priority Mask Register |
External | GICC_RPR | CPU Interface Running Priority Register |
External | GICC_STATUSR | CPU Interface Status Register |
Exec state | Name | Description |
---|---|---|
External | GICV_ABPR | Virtual Machine Aliased Binary Point Register |
External | GICV_AEOIR | Virtual Machine Aliased End Of Interrupt Register |
External | GICV_AHPPIR | Virtual Machine Aliased Highest Priority Pending Interrupt Register |
External | GICV_AIAR | Virtual Machine Aliased Interrupt Acknowledge Register |
External | GICV_APR<n> | Virtual Machine Active Priorities Registers |
External | GICV_BPR | Virtual Machine Binary Point Register |
External | GICV_CTLR | Virtual Machine Control Register |
External | GICV_DIR | Virtual Machine Deactivate Interrupt Register |
External | GICV_EOIR | Virtual Machine End Of Interrupt Register |
External | GICV_HPPIR | Virtual Machine Highest Priority Pending Interrupt Register |
External | GICV_IAR | Virtual Machine Interrupt Acknowledge Register |
External | GICV_IIDR | Virtual Machine CPU Interface Identification Register |
External | GICV_PMR | Virtual Machine Priority Mask Register |
External | GICV_RPR | Virtual Machine Running Priority Register |
External | GICV_STATUSR | Virtual Machine Error Reporting Status Register |
Exec state | Name | Description |
---|---|---|
External | GICH_APR<n> | Active Priorities Registers |
External | GICH_EISR | End Interrupt Status Register |
External | GICH_ELRSR | Empty List Register Status Register |
External | GICH_HCR | Hypervisor Control Register |
External | GICH_LR<n> | List Registers |
External | GICH_MISR | Maintenance Interrupt Status Register |
External | GICH_VMCR | Virtual Machine Control Register |
External | GICH_VTR | Virtual Type Register |
Exec state | Name | Description |
---|---|---|
External | GITS_BASER<n> | ITS Translation Table Descriptors |
External | GITS_CBASER | ITS Command Queue Descriptor |
External | GITS_CREADR | ITS Read Register |
External | GITS_CTLR | ITS Control Register |
External | GITS_CWRITER | ITS Write Register |
External | GITS_IIDR | ITS Identification Register |
External | GITS_MPAMIDR | Report maximum PARTID and PMG Register |
External | GITS_PARTIDR | Set PARTID and PMG Register |
External | GITS_TRANSLATER | ITS Translation Register |
External | GITS_TYPER | ITS Type Register |
Exec state | Name | Description |
---|---|---|
External | GITS_BASER<n> | ITS Translation Table Descriptors |
External | GITS_CBASER | ITS Command Queue Descriptor |
External | GITS_CREADR | ITS Read Register |
External | GITS_CTLR | ITS Control Register |
External | GITS_CWRITER | ITS Write Register |
External | GITS_IIDR | ITS Identification Register |
External | GITS_MPAMIDR | Report maximum PARTID and PMG Register |
External | GITS_PARTIDR | Set PARTID and PMG Register |
External | GITS_TRANSLATER | ITS Translation Register |
External | GITS_TYPER | ITS Type Register |
12/01/2022 09:56
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