DBGDTR2B, Debug Data Transfer Register 2B

The DBGDTR2B characteristics are:

Purpose

Allows external debuggers to access capability state within PE. Transfers higher 32 bits of the upper half of capabilities. It is a component of the Debug Communications Channel.

Configuration

External register DBGDTR2B bits [31:0] are architecturally mapped to AArch64 System register CDBGDTR_EL0[127:96] .

DBGDTR2B is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

This register is present only when Morello is implemented. Otherwise, direct accesses to DBGDTR2B are RES0.

Attributes

DBGDTR2B is a 32-bit register.

Field descriptions

The DBGDTR2B bit assignments are:

313029282726252423222120191817161514131211109876543210
DTR2B

Bits [31:0]

Data transfer register for bits 127:96 of capability tranfers.

On a Cold reset, this field resets to an UNKNOWN value.

Accessing the DBGDTR2B

If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:

DBGDTR2B can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x044DBGDTR2B

This interface is accessible as follows:




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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