The GICH_EISR characteristics are:
Indicates which List registers have outstanding EOI maintenance interrupts.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_EISR is a 32-bit register.
The GICH_EISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Status<n>, bit [n], for n = 0 to 15 |
Reserved, RES0.
EOI maintenance interrupt status for List register <n>:
Status<n> | Meaning |
---|---|
0b0 |
GICH_LR<n> does not have an EOI maintenance interrupt. |
0b1 |
GICH_LR<n> has an EOI maintenance interrupt that has not been handled. |
For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:
This field resets to an architecturally UNKNOWN value.
This register is used only when System register access is not enabled. When System register access is enabled:
Bits corresponding to unimplemented List registers are RAZ.
Component | Offset | Instance |
---|---|---|
GIC Virtual interface control | 0x0020 | GICH_EISR |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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