CCTLR_EL0, Capability Control Register (EL0)

The CCTLR_EL0 characteristics are:

Purpose

Provides control of capability-related functionality at EL0.

Configuration

This register is present only when Morello is implemented. Otherwise, direct accesses to CCTLR_EL0 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CCTLR_EL0 is a 64-bit register.

Field descriptions

The CCTLR_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0SBLPERMVCTRES0ADRDPBPCCBODDCBORES0
313029282726252423222120191817161514131211109876543210

Bits [63:8]

Reserved, RES0.

SBL, bit [7]

Controls whether branch-and-link instructions at EL0 seal the capability generated in C30.

Controls whether the following instructions at EL0 require a target capability with ObjectType set to 1:

BLRR, BLRS (capability), BRR, BRS (capability), RETR, RETS (capability).

SBLMeaning
0b0

Branch-and-link instructions which generate a capability in C30 do not seal the capability.

The specified instructions do not require a target capability with ObjectType set to 1.

0b1

Branch-and-link instructions which generate a capability in C30 seal the generated capability with ObjectType set to 1.

The specified instructions require a target capability with ObjectType set to 1.

This field resets to an architecturally UNKNOWN value.

PERMVCT, bit [6]

Permits access to CNTVCT_EL0 without PCC System permission at EL0

PERMVCTMeaning
0b0

Access to CNTVCT_EL0 at EL0 requires PCC System permission

0b1

This field has no effect

This field resets to an architecturally UNKNOWN value.

Bit [5]

Reserved, RES0.

ADRDPB, bit [4]

ADRDP instruction base register selection at EL0

ADRDPBMeaning
0b0

ADRDP uses DDC as a base register

0b1

ADRDP uses C28 as a base register

This field resets to an architecturally UNKNOWN value.

PCCBO, bit [3]

PCC base offset enable for A64 instructions writing PC or generating a PC derived 64-bit value at EL0

PCCBOMeaning
0b0

Accesses do not add PCC base to the address written to PC, and do not subtract PCC base from the address read from PCC.

0b1

Accesses add PCC base to the address written to PC, and subtract PCC base from the address read from PCC.

Note: this affects the following instructions:

This field resets to an architecturally UNKNOWN value.

DDCBO, bit [2]

DDC base offset enable for accesses using a 64-bit base register at EL0

DDCBOMeaning
0b0

Accesses do not add or subtract DDC base from the accessed address.

0b1

Accesses add or subtract DDC base from the accessed address, depending on the instruction.

This field resets to an architecturally UNKNOWN value.

Bits [1:0]

Reserved, RES0.

Accessing the CCTLR_EL0

Accesses to this register use the following encodings:

MRS <Xt>, CCTLR_EL0

op0op1CRnCRmop2
0b110b0110b00010b00100b010

if PSTATE.EL == EL0 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.CEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x29); else AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.CEN != '11' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL0; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL0; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL0; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL0;

MSR CCTLR_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b00010b00100b010

if PSTATE.EL == EL0 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.CEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x29); else AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.CEN != '11' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL0 = X[t]; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL0 = X[t]; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL0 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL0 = X[t];




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.