The MDCR_EL2 characteristics are:
Provides EL2 configuration options for self-hosted debug and the Performance Monitors Extension.
AArch64 System register MDCR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HDCR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
MDCR_EL2 is a 64-bit register.
The MDCR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | HPMD | RES0 | TPMS | E2PB | TDRA | TDOSA | TDA | TDE | HPME | TPM | TPMCR | HPMN | |||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Guest Performance Monitors Disable. This control prohibits event counting at EL2.
HPMD | Meaning |
---|---|
0b0 |
Event counting allowed at EL2. |
0b1 |
Event counting prohibited at EL2. If ARMv8.2-Debug is not implemented, event counting is prohibited unless enabled by the IMPLEMENTATION DEFINED authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
This control applies only to:
The other event counters are unaffected, and when PMCR_EL0.DP is set to 0, PMCCNTR_EL0 is unaffected.
On a Warm reset, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap Performance Monitor Sampling. When EL2 is enabled in the current Security state, this field controls access to Statistical Profiling control registers from EL1.
TPMS | Meaning |
---|---|
0b0 |
Do not trap Statistical Profiling controls to EL2. |
0b1 |
Accesses to Statistical Profiling controls at EL1 generate a Trap exception to EL2 when EL2 is enabled in the current Security state. |
The Statistical Profiling control registers trapped by this control are: PMSCR_EL1, PMSEVFR_EL1, PMSFCR_EL1, PMSICR_EL1, PMSIDR_EL1, PMSIRR_EL1, and PMSLATFR_EL1.
Reserved, RES0.
EL2 Profiling Buffer. If EL2 is implemented and enabled in the Profiling Buffer owning Security state, this field controls the owning translation regime. If EL2 is implemented and enabled in the current Security state, this field controls access to Profiling Buffer control registers from EL1.
E2PB | Meaning |
---|---|
0b00 |
If EL2 is implemented and enabled in the Profiling Buffer owning Security state, the Profiling Buffer uses the EL2 or EL2&0 stage 1 translation regime. Otherwise the Profiling Buffer uses the EL1&0 stage 1 translation regime. If EL2 is implemented and enabled in the current Security state, accesses to Profiling Buffer control registers at EL1 generate a Trap exception to EL2. |
0b10 |
Profiling Buffer uses the EL1&0 stage 1 translation regime. If EL2 is implemented and enabled in the current Security state, accesses to Profiling Buffer control registers at EL1 generate a Trap exception to EL2. |
0b11 |
Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling Buffer control registers at EL1 are not trapped to EL2. |
All other values are reserved.
The Profiling Buffer control registers trapped by this control are: PMBLIMITR_EL1, PMBPTR_EL1, and PMBSR_EL1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap Debug ROM Address register access. Traps System register accesses to the Debug ROM registers to EL2 when EL2 is enabled in the current Security state as follows:
TDRA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL0 and EL1 System register accesses to the Debug ROM registers are trapped to EL2 when EL2 is enabled in the current Security state, unless it is trapped by DBGDSCRext.UDCCdis or MDSCR_EL1.TDCC. |
This field is treated as being 1 for all purposes other than a direct read when one or more of the following are true:
EL2 does not provide traps on debug register accesses through the optional memory-mapped external debug interfaces.
System register accesses to the debug registers might have side-effects. When a System register access is trapped to EL2, no side-effects occur before the exception is taken to EL2.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap debug OS-related register access. Traps EL1 System register accesses to the powerdown debug registers to EL2, from both Execution states as follows:
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 System register accesses to the powerdown debug registers are trapped to EL2 when EL2 is enabled in the current Security state. |
These registers are not accessible at EL0.
This field is treated as being 1 for all purposes other than a direct read when one or more of the following are true:
System register accesses to the debug registers might have side-effects. When a System register access is trapped to EL2, no side-effects occur before the exception is taken to EL2.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap debug OS-related register access. Traps EL1 System register accesses to the powerdown debug registers to EL2, from both Execution states as follows:
In AArch64 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x18:
OSLAR_EL1, OSLSR_EL1, and DBGPRCR_EL1.
Any IMPLEMENTATION DEFINED register with similar functionality that the implementation specifies as trapped by this bit.
In AArch32 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x05:
It is IMPLEMENTATION DEFINED whether accesses to OSDLR_EL1 are trapped and DBGOSDLR are trapped.
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 System register accesses to the powerdown debug registers are trapped to EL2 when EL2 is enabled in the current Security state. |
These registers are not accessible at EL0.
This field is treated as being 1 for all purposes other than a direct read when one or more of the following are true:
EL2 does not provide traps on debug register accesses through the optional memory-mapped external debug interfaces.
System register accesses to the debug registers might have side-effects. When a System register access is trapped to EL2, no side-effects occur before the exception is taken to EL2.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap Debug Access. Traps EL0 and EL1 System register accesses to debug System registers that are not trapped by MDCR_EL2.TDRA or MDCR_EL2.TDOSA, as follows:
TDA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL0 or EL1 System register accesses to the debug registers are trapped from both Execution states to EL2 when EL2 is enabled in the current Security state, unless the access generates a higher priority exception. |
Traps of AArch32 accesses to DBGDTRRXint and DBGDTRTXint are ignored in Debug state.
Traps of AArch64 accesses to DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0 are ignored in Debug state.
This field is treated as being 1 for all purposes other than a direct read when one or more of the following are true:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Trap Debug exceptions.
TDE | Meaning |
---|---|
0b0 |
This control has no effect on the routing of debug exceptions, and has no effect on accesses to debug registers. |
0b1 |
Debug exceptions generated at EL1 or EL0 are routed to EL2 when EL2 is enabled in the current Security state. The MDCR_EL2.{TDRA, TDOSA, TDA} fields are treated as being 1 for all purposes other than returning the result of a direct read of the register. |
This field is treated as being 1 for all purposes other than a direct read when HCR_EL2.TGE == 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
[MDCR_EL2.HPMN..(N-1)] event counters enable.
HPME | Meaning |
---|---|
0b0 |
Event counters in the range [MDCR_EL2.HPMN..(PMCR_EL0.N-1)] are disabled. |
0b1 |
Event counters in the range [MDCR_EL2.HPMN..(PMCR_EL0.N-1)] are enabled by PMCNTENSET_EL0. |
If MDCR_EL2.HPMN is less than PMCR_EL0.N or PMCR.N, the event counters in the range [MDCR_EL2.HPMN..(PMCR_EL0.N-1)] or [HDCR.HPMN..(PMCR.N-1)], are enabled and disabled by this bit. Otherwise this bit has no effect on the operation of the event counters.
The effect of MDCR_EL2.HPMN on the operation of this bit applies regardless of whether EL2 is enabled in the current Security state.
For more information see the description of the HPMN field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap Performance Monitors accesses. Traps EL0 and EL1 accesses to all Performance Monitor registers to EL2 when EL2 is enabled in the current Security state, from both Execution states, as follows:
In AArch64 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x18:
In AArch32 state, MRC or MCR accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x03, MRRC or MCRR accesses are trapped to EL2 and reported using EC syndrome value 0x04:
If ARMv8.4-PMU is implemented, in AArch64 state, PMMIR_EL1 and in AArch32 state, PMMIR.
If ARMv8.1-PMU is implemented, in AArch32 state, PMCEID2, and PMCEID3.
TPM | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL0 and EL1 accesses to all Performance Monitor registers are trapped to EL2 when EL2 is enabled in the current Security state. |
EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap PMCR_EL0 or PMCR accesses. Traps EL0 and EL1 accesses to EL2, when EL2 is enabled in the current Security state, as follows:
In AArch64 state, accesses to PMCR_EL0 are trapped to EL2, reported using EC syndrome value 0x18.
In AArch32 state, accesses to PMCR are trapped to EL2, reported using EC syndrome value 0x03.
TPMCR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL0 and EL1 accesses to the PMCR_EL0 or PMCR are trapped to EL2 when EL2 is enabled in the current Security state, unless it is trapped by PMUSERENR.EN or PMUSERENR_EL0.EN. |
EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Defines the number of event counters that are accessible from EL3, EL2, EL1, and from EL0 if permitted.
If HPMN is less than PMCR_EL0.N, HPMN divides the Performance Monitors into two ranges: [0..(HPMN-1)] and [HPMN..(PMCR_EL0.N-1)].
For an event counter in the range [0..(HPMN-1)]:
If HPMN is equal to PMCR_EL0.N, this applies to all event counters.
If HPMN is less than PMCR_EL0.N, for an event counter in the range [HPMN..(PMCR_EL0.N-1)]:
If this field is set to 0, or to a value larger than PMCR_EL0.N, then the following CONSTRAINED UNPREDICTABLE behaviors apply:
On a Warm reset, this field resets to the value in PMCR_EL0.N.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCR_EL2; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else MDCR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else MDCR_EL2 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.