CDBGDTR_EL0, Capability Debug Data Transfer Register, half-duplex

The CDBGDTR_EL0 characteristics are:

Purpose

Transfers 129 bits of data between the PE and an external debugger. Can transfer both ways using only a single register.

Configuration

AArch64 System register CDBGDTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register DBGDTR_EL0[63:0] .

AArch64 System register CDBGDTR_EL0 bit [128] is architecturally mapped to External register EDSCR2.

AArch64 System register CDBGDTR_EL0 bits [127:96] are architecturally mapped to External register DBGDTR2B[31:0] .

AArch64 System register CDBGDTR_EL0 bits [95:64] are architecturally mapped to External register DBGDTR2A[31:0] .

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when written.

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when read.

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when read.

AArch64 System register CDBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when read.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when read.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when read.

AArch64 System register CDBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when read.

This register is present only when Morello is implemented. Otherwise, direct accesses to CDBGDTR_EL0 are UNDEFINED.

Attributes

CDBGDTR_EL0 is a 129-bit register.

Field descriptions

The CDBGDTR_EL0 bit assignments are:

Bits [128:0]

Writes to this register set:

If RXfull is set to 1, reads of this register return:

If RXfull is set to 0, reads of this register return an UNKNOWN value.

After the read, RXfull is cleared to 0.

Accessing the CDBGDTR_EL0

Accesses to this register use the following encodings:

MRS <Ct>, CDBGDTR_EL0

op0op1CRnCRmop2
0b100b0110b00000b01000b000

if !Halted() then UNDEFINED; elsif PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.CEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x29); else AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.CEN != '11' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CDBGDTR_EL0; elsif PSTATE.EL == EL1 then if CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CDBGDTR_EL0; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CDBGDTR_EL0; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CDBGDTR_EL0;

MSR CDBGDTR_EL0, <Ct>

op0op1CRnCRmop2
0b100b0110b00000b01000b000

if !Halted() then UNDEFINED; elsif PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.CEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x29); else AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.CEN != '11' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CDBGDTR_EL0 = C[t]; elsif PSTATE.EL == EL1 then if CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CDBGDTR_EL0 = C[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CDBGDTR_EL0 = C[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CDBGDTR_EL0 = C[t];




12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b

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