The ID_AA64MMFR0_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
ID_AA64MMFR0_EL1 is a 64-bit register.
The ID_AA64MMFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | ExS | TGran4_2 | TGran64_2 | TGran16_2 | |||||||||||||||||||||||||||
TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Support for disabling context synchronizing exception entry and exit. Defined values are:
ExS | Meaning |
---|---|
0b0000 |
All exception entries and exits are context synchronization events. |
0b0001 |
Non-context synchronizing exception entry and exit are supported. |
All other values are reserved.
ARMv8.5-CSEH implements the functionality identified by the value 0b0001.
Reserved, RES0.
Support for 4KB memory granule size for stage 2. Defined values are:
TGran4_2 | Meaning |
---|---|
0b0000 |
4KB Stage 2 granule is identified in the TGran4 field |
0b0001 |
4KB granule not supported at stage 2 |
0b0010 |
4KB granule supported at stage 2 |
All other values are reserved.
The 0b0000 value is deprecated.
Reserved, RES0.
Support for 64KB memory granule size for stage 2. Defined values are:
TGran64_2 | Meaning |
---|---|
0b0000 |
64KB Stage 2 granule is identified in the TGran64 field |
0b0001 |
64KB granule not supported at stage 2 |
0b0010 |
64KB granule supported at stage 2 |
All other values are reserved.
The 0b0000 value is deprecated.
Reserved, RES0.
Support for 16KB memory granule size for stage 2. Defined values are:
TGran16_2 | Meaning |
---|---|
0b0000 |
16KB Stage 2 granule is identified in the TGran16 field |
0b0001 |
16KB granule not supported at stage 2 |
0b0010 |
16KB granule supported at stage 2 |
All other values are reserved.
The 0b0000 value is deprecated.
Reserved, RES0.
Support for 4KB memory translation granule size. Defined values are:
TGran4 | Meaning |
---|---|
0b0000 |
4KB granule supported. |
0b1111 |
4KB granule not supported. |
All other values are reserved.
Support for 64KB memory translation granule size. Defined values are:
TGran64 | Meaning |
---|---|
0b0000 |
64KB granule supported. |
0b1111 |
64KB granule not supported. |
All other values are reserved.
Support for 16KB memory translation granule size. Defined values are:
TGran16 | Meaning |
---|---|
0b0000 |
16KB granule not supported. |
0b0001 |
16KB granule supported. |
All other values are reserved.
Mixed-endian support at EL0 only. Defined values are:
BigEndEL0 | Meaning |
---|---|
0b0000 |
No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. |
0b0001 |
Mixed-endian support at EL0. The SCTLR_EL1.E0E bit can be configured. |
All other values are reserved.
This field is invalid and is RES0 if the BigEnd field, bits [11:8], is not 0b0000.
Secure versus Non-secure Memory distinction. Defined values are:
SNSMem | Meaning |
---|---|
0b0000 |
Does not support a distinction between Secure and Non-secure Memory. |
0b0001 |
Does support a distinction between Secure and Non-secure Memory. |
All other values are reserved.
Mixed-endian configuration support. Defined values are:
BigEnd | Meaning |
---|---|
0b0000 |
No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field, bits[19:16], for whether EL0 supports mixed-endian. |
0b0001 |
Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured. |
All other values are reserved.
Number of ASID bits. Defined values are:
ASIDBits | Meaning |
---|---|
0b0000 |
8 bits. |
0b0010 |
16 bits. |
All other values are reserved.
Physical Address range supported. Defined values are:
PARange | Meaning |
---|---|
0b0000 |
32 bits, 4GB. |
0b0001 |
36 bits, 64GB. |
0b0010 |
40 bits, 1TB. |
0b0011 |
42 bits, 4TB. |
0b0100 |
44 bits, 16TB. |
0b0101 |
48 bits, 256TB. |
0b0110 |
52 bits, 4PB. |
All other values are reserved.
The value 0b0110 is permitted only if the implementation includes ARMv8.2-LPA, otherwise it is reserved.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64MMFR0_EL1; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); else return ID_AA64MMFR0_EL1; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); else return ID_AA64MMFR0_EL1;
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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