The CCTLR_EL2 characteristics are:
Provides control of capability-related functionality at EL2.
This register is present only when Morello is implemented. Otherwise, direct accesses to CCTLR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
CCTLR_EL2 is a 64-bit register.
The CCTLR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | SBL | PERMVCT | C64E | ADRDPB | PCCBO | DDCBO | TGEN1 | TGEN0 | |||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Controls whether branch-and-link instructions at EL2 seal the capability generated in C30.
Controls whether the following instructions at EL2 require a target capability with ObjectType set to 1:
BLRR, BLRS (capability), BRR, BRS (capability), RETR, RETS (capability).
SBL | Meaning |
---|---|
0b0 |
Branch-and-link instructions which generate a capability in C30 do not seal the capability. The specified instructions do not require a target capability with ObjectType set to 1. |
0b1 |
Branch-and-link instructions which generate a capability in C30 seal the generated capability with ObjectType set to 1. The specified instructions require a target capability with ObjectType set to 1. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Permits access to CNTVCT_EL0 without PCC System permission at EL2
PERMVCT | Meaning |
---|---|
0b0 |
Access to CNTVCT_EL0 at EL2 requires PCC System permission |
0b1 |
This field has no effect |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Capability mode on exception entry to EL2
C64E | Meaning |
---|---|
0b0 |
On exception entry PSTATE.C64 is set to 0. |
0b1 |
On exception entry PSTATE.C64 is set to 1. |
In a system where the PE resets into EL2, this field resets to 0.
ADRDP instruction base register selection at EL2
ADRDPB | Meaning |
---|---|
0b0 |
ADRDP uses DDC as a base register |
0b1 |
ADRDP uses C28 as a base register |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
PCC base offset enable for A64 instructions writing PC or generating a PC derived 64-bit value at EL2
PCCBO | Meaning |
---|---|
0b0 |
Accesses do not add PCC base to the address written to PC, and do not subtract PCC base from the address read from PCC. |
0b1 |
Accesses add PCC base to the address written to PC, and subtract PCC base from the address read from PCC. |
Note: this affects the following instructions:
BR Xn
RET Xn
BL imm (the value written to LR)
BLR Xn (both the Xn and LR values)
ADR(P) Xd, label
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
DDC base offset enable for accesses using a 64-bit base register at EL2
DDCBO | Meaning |
---|---|
0b0 |
Accesses do not add or subtract DDC base from the accessed address. |
0b1 |
Accesses add or subtract DDC base from the accessed address, depending on the instruction. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Tag generation bit for TTBR1_EL2 based accesses
TGEN1 | Meaning |
---|---|
0b0 |
Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b11. |
0b1 |
Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b10. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Tag generation bit for TTBR0_EL2 based accesses
TGEN0 | Meaning |
---|---|
0b0 |
Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b11. |
0b1 |
Generates a fault when loading a valid capability from memory where the Block and Page descriptor LC field is 0b10. |
In a system where the PE resets into EL2, this field resets to an architecturally UNKNOWN value.
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CCTLR_EL2 or CCTLR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL2; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL2 = X[t];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0001 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL1; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); elsif HCR_EL2.E2H == '1' then return CCTLR_EL2; else return CCTLR_EL1; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else return CCTLR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0001 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL1 then AArch64.SystemAccessTrap(EL1, 0x18); elsif TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.CEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then if TargetELForCapabilityExceptions() == EL2 then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '0' && CPTR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HCR_EL2.E2H == '1' && CPTR_EL2.CEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x29); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); elsif HCR_EL2.E2H == '1' then CCTLR_EL2 = X[t]; else CCTLR_EL1 = X[t]; elsif PSTATE.EL == EL3 then if IsFeatureImplemented("Morello") && !CapIsSystemAccessEnabled() && !Halted() then AArch64.SystemAccessTrap(EL3, 0x18); elsif CPTR_EL3.EC == '0' then AArch64.SystemAccessTrap(EL3, 0x29); else CCTLR_EL1 = X[t];
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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