The PMEVTYPER<n>_EL0 characteristics are:
Configures event counter n, where n is 0 to 30.
External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[31:0] .
External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0] .
PMEVTYPER<n>_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
If event counter n is not implemented then accesses to this register are:
PMEVTYPER<n>_EL0 is a 32-bit register.
The PMEVTYPER<n>_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | MT | RES0 | evtCount[15:10] | evtCount[9:0] |
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMEVTYPER<n>_EL0.NSK bit.
P | Meaning |
---|---|
0b0 |
Count events in EL1. |
0b1 |
Do not count events in EL1. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMEVTYPER<n>_EL0.NSU bit.
U | Meaning |
---|---|
0b0 |
Count events in EL0. |
0b1 |
Do not count events in EL0. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
NSH | Meaning |
---|---|
0b0 |
Do not count events in EL2. |
0b1 |
Count events in EL2. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Secure EL3 filtering bit.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Secure EL3 are counted.
Otherwise, events in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0b0.
This field is not visible in the AArch32 PMEVTYPER<n> System register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Multithreading.
MT | Meaning |
---|---|
0b0 |
Count events only on controlling PE. |
0b1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Extension to evtCount[9:0]. See evtCount[9:0] for more details.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Event to count. The event number of the event that is counted by event counter PMEVCNTR<n>_EL0.
Software must program this field with an event that is supported by the PE being programmed.
The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.
If evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:
UNPREDICTABLE means the event must not expose privileged information.
Arm recommends that the behavior across a family of implementations is defined such that if a given implementation does not include an event from a set of common IMPLEMENTATION DEFINED events, then no event is counted and the value read back on evtCount is the value written.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0x400 + 4n | PMEVTYPER<n>_EL0 |
This interface is accessible as follows:
12/01/2022 09:56; 05a4944b4b04e7ab50def8c126b479d22136f35b
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