_mm_fixupimm_sd
Classification
AVX-512, Miscellaneous, CPUID Test: AVX512F
Header File
Instruction
VFIXUPIMMSD xmm, xmm, xmm, imm8
Synopsis
_mm_fixupimm_sd(__m128d a, __m128d b, __m128i c, int imm8);
Description
Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting.
Operation
enum TOKEN_TYPE {
QNAN_TOKEN := 0, \
SNAN_TOKEN := 1, \
ZERO_VALUE_TOKEN := 2, \
ONE_VALUE_TOKEN := 3, \
NEG_INF_TOKEN := 4, \
POS_INF_TOKEN := 5, \
NEG_VALUE_TOKEN := 6, \
POS_VALUE_TOKEN := 7
}
DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
CASE(tsrc[63:0]) OF
QNAN_TOKEN:j := 0
SNAN_TOKEN:j := 1
ZERO_VALUE_TOKEN: j := 2
ONE_VALUE_TOKEN: j := 3
NEG_INF_TOKEN: j := 4
POS_INF_TOKEN: j := 5
NEG_VALUE_TOKEN: j := 6
POS_VALUE_TOKEN: j := 7
ESAC
token_response[3:0] := src3[3+4*j:4*j]
CASE(token_response[3:0]) OF
0 : dest[63:0] := src1[63:0]
1 : dest[63:0] := tsrc[63:0]
2 : dest[63:0] := QNaN(tsrc[63:0])
3 : dest[63:0] := QNAN_Indefinite
4 : dest[63:0] := -INF
5 : dest[63:0] := +INF
6 : dest[63:0] := tsrc.sign? -INF : +INF
7 : dest[63:0] := -0
8 : dest[63:0] := +0
9 : dest[63:0] := -1
10: dest[63:0] := +1
11: dest[63:0] := 1/2
12: dest[63:0] := 90.0
13: dest[63:0] := PI/2
14: dest[63:0] := MAX_FLOAT
15: dest[63:0] := -MAX_FLOAT
ESAC
CASE(tsrc[31:0]) OF
ZERO_VALUE_TOKEN:
IF (imm8[0]) #ZE; FI
ZERO_VALUE_TOKEN:
IF (imm8[1]) #IE; FI
ONE_VALUE_TOKEN:
IF (imm8[2]) #ZE; FI
ONE_VALUE_TOKEN:
IF (imm8[3]) #IE; FI
SNAN_TOKEN:
IF (imm8[4]) #IE; FI
NEG_INF_TOKEN:
IF (imm8[5]) #IE; FI
NEG_VALUE_TOKEN:
IF (imm8[6]) #IE; FI
POS_INF_TOKEN:
IF (imm8[7]) #IE; FI
ESAC
RETURN dest[63:0]
}
dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
dst[127:64] := a[127:64]
dst[MAX:128] := 0