_mm_maskz_range_round_ss
Classification
AVX-512, Miscellaneous, CPUID Test: AVX512DQ
Header File
immintrin.h
Instruction
VRANGESS xmm {z}, xmm, xmm {sae}, imm8
Synopsis
 _mm_maskz_range_round_ss(__mmask8 k, __m128 a, __m128 b, int imm8, int sae);
Description
Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]
Operation
DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
	CASE opCtl[1:0] OF
	0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0]
	1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0]
	2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
	3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
	ESAC
	
	CASE signSelCtl[1:0] OF
	0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0])
	1: dst[31:0] := tmp[31:0]
	2: dst[31:0] := (0 << 31) OR (tmp[30:0])
	3: dst[31:0] := (1 << 31) OR (tmp[30:0])
	ESAC
	
	RETURN dst
}
IF k[0]
	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
ELSE
	dst[31:0] := 0
FI
dst[127:32] := a[127:32]
dst[MAX:128] := 0