Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. More...

Modules

 Core register bit field macros
 Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 

Detailed Description

Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.

Therefore they are not covered by the Cortex-M0+ header file.