29#ifndef __CMSIS_ICCARM_H__
30#define __CMSIS_ICCARM_H__
33 #error This file should only be compiled by ICCARM
38#define __IAR_FT _Pragma("inline=forced") __intrinsic
40#if (__VER__ >= 8000000)
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #elif (__VER__ >= 7080000)
51 #define __ALIGNED(x) __attribute__((aligned(x)))
53 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
61#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
64 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65 #define __ARM_ARCH_8M_MAIN__ 1
66 #elif defined(__ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
70 #define __ARM_ARCH_6M__ 1
73 #define __ARM_ARCH_7EM__ 1
75 #define __ARM_ARCH_7M__ 1
82#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85 #define __ARM_ARCH_6M__ 1
86 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87 #define __ARM_ARCH_7M__ 1
88 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89 #define __ARM_ARCH_7EM__ 1
90 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91 #define __ARM_ARCH_8M_BASE__ 1
92 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
94 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95 #define __ARM_ARCH_8M_MAIN__ 1
97 #error "Unknown target."
103#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104 #define __IAR_M0_FAMILY 1
105#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106 #define __IAR_M0_FAMILY 1
108 #define __IAR_M0_FAMILY 0
116#ifndef __COMPILER_BARRIER
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
121 #define __INLINE inline
126 #define __NO_RETURN __attribute__((__noreturn__))
128 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
134 #define __PACKED __attribute__((packed, aligned(1)))
137 #define __PACKED __packed
141#ifndef __PACKED_STRUCT
143 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
146 #define __PACKED_STRUCT __packed struct
150#ifndef __PACKED_UNION
152 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
155 #define __PACKED_UNION __packed union
161 #define __RESTRICT __restrict
164 #define __RESTRICT restrict
168#ifndef __STATIC_INLINE
169 #define __STATIC_INLINE static inline
173 #define __FORCEINLINE _Pragma("inline=forced")
176#ifndef __STATIC_FORCEINLINE
177 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
180#ifndef __UNALIGNED_UINT16_READ
182#pragma language=extended
183__IAR_FT uint16_t __iar_uint16_read(
void const *ptr)
185 return *(__packed uint16_t*)(ptr);
187#pragma language=restore
188#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
192#ifndef __UNALIGNED_UINT16_WRITE
194#pragma language=extended
195__IAR_FT
void __iar_uint16_write(
void const *ptr, uint16_t val)
197 *(__packed uint16_t*)(ptr) = val;;
199#pragma language=restore
200#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
203#ifndef __UNALIGNED_UINT32_READ
205#pragma language=extended
206__IAR_FT uint32_t __iar_uint32_read(
void const *ptr)
208 return *(__packed uint32_t*)(ptr);
210#pragma language=restore
211#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
214#ifndef __UNALIGNED_UINT32_WRITE
216#pragma language=extended
217__IAR_FT
void __iar_uint32_write(
void const *ptr, uint32_t val)
219 *(__packed uint32_t*)(ptr) = val;;
221#pragma language=restore
222#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
225#ifndef __UNALIGNED_UINT32
227#pragma language=extended
229#pragma language=restore
230#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
235 #define __USED __attribute__((used))
237 #define __USED _Pragma("__root")
243 #define __WEAK __attribute__((weak))
245 #define __WEAK _Pragma("__weak")
249#ifndef __PROGRAM_START
250#define __PROGRAM_START __iar_program_start
254#define __INITIAL_SP CSTACK$$Limit
258#define __STACK_LIMIT CSTACK$$Base
261#ifndef __VECTOR_TABLE
262#define __VECTOR_TABLE __vector_table
265#ifndef __VECTOR_TABLE_ATTRIBUTE
266#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
269#ifndef __ICCARM_INTRINSICS_VERSION__
270 #define __ICCARM_INTRINSICS_VERSION__ 0
273#if __ICCARM_INTRINSICS_VERSION__ == 2
291 #include "iccarm_builtin.h"
293 #define __disable_fault_irq __iar_builtin_disable_fiq
294 #define __disable_irq __iar_builtin_disable_interrupt
295 #define __enable_fault_irq __iar_builtin_enable_fiq
296 #define __enable_irq __iar_builtin_enable_interrupt
297 #define __arm_rsr __iar_builtin_rsr
298 #define __arm_wsr __iar_builtin_wsr
301 #define __get_APSR() (__arm_rsr("APSR"))
302 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
303 #define __get_CONTROL() (__arm_rsr("CONTROL"))
304 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
306 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
307 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
308 #define __get_FPSCR() (__arm_rsr("FPSCR"))
309 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
311 #define __get_FPSCR() ( 0 )
312 #define __set_FPSCR(VALUE) ((void)VALUE)
315 #define __get_IPSR() (__arm_rsr("IPSR"))
316 #define __get_MSP() (__arm_rsr("MSP"))
317 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
318 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
320 #define __get_MSPLIM() (0U)
322 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
324 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
325 #define __get_PSP() (__arm_rsr("PSP"))
327 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
328 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
330 #define __get_PSPLIM() (0U)
332 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
335 #define __get_xPSR() (__arm_rsr("xPSR"))
337 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
338 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
339 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
340 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
341 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
343 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
344 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
346 #define __set_MSPLIM(VALUE) ((void)(VALUE))
348 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
350 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
351 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
352 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
353 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
355 #define __set_PSPLIM(VALUE) ((void)(VALUE))
357 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
360 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
361 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
362 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
363 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
364 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
365 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
366 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
367 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
368 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
369 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
370 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
371 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
372 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
373 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
375 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
376 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
378 #define __TZ_get_PSPLIM_NS() (0U)
379 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
381 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
382 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
385 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
386 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
388 #define __NOP __iar_builtin_no_operation
390 #define __CLZ __iar_builtin_CLZ
391 #define __CLREX __iar_builtin_CLREX
393 #define __DMB __iar_builtin_DMB
394 #define __DSB __iar_builtin_DSB
395 #define __ISB __iar_builtin_ISB
397 #define __LDREXB __iar_builtin_LDREXB
398 #define __LDREXH __iar_builtin_LDREXH
399 #define __LDREXW __iar_builtin_LDREX
401 #define __RBIT __iar_builtin_RBIT
402 #define __REV __iar_builtin_REV
403 #define __REV16 __iar_builtin_REV16
405 __IAR_FT int16_t
__REVSH(int16_t val)
407 return (int16_t) __iar_builtin_REVSH(val);
410 #define __ROR __iar_builtin_ROR
411 #define __RRX __iar_builtin_RRX
413 #define __SEV __iar_builtin_SEV
416 #define __SSAT __iar_builtin_SSAT
419 #define __STREXB __iar_builtin_STREXB
420 #define __STREXH __iar_builtin_STREXH
421 #define __STREXW __iar_builtin_STREX
424 #define __USAT __iar_builtin_USAT
427 #define __WFE __iar_builtin_WFE
428 #define __WFI __iar_builtin_WFI
431 #define __SADD8 __iar_builtin_SADD8
432 #define __QADD8 __iar_builtin_QADD8
433 #define __SHADD8 __iar_builtin_SHADD8
434 #define __UADD8 __iar_builtin_UADD8
435 #define __UQADD8 __iar_builtin_UQADD8
436 #define __UHADD8 __iar_builtin_UHADD8
437 #define __SSUB8 __iar_builtin_SSUB8
438 #define __QSUB8 __iar_builtin_QSUB8
439 #define __SHSUB8 __iar_builtin_SHSUB8
440 #define __USUB8 __iar_builtin_USUB8
441 #define __UQSUB8 __iar_builtin_UQSUB8
442 #define __UHSUB8 __iar_builtin_UHSUB8
443 #define __SADD16 __iar_builtin_SADD16
444 #define __QADD16 __iar_builtin_QADD16
445 #define __SHADD16 __iar_builtin_SHADD16
446 #define __UADD16 __iar_builtin_UADD16
447 #define __UQADD16 __iar_builtin_UQADD16
448 #define __UHADD16 __iar_builtin_UHADD16
449 #define __SSUB16 __iar_builtin_SSUB16
450 #define __QSUB16 __iar_builtin_QSUB16
451 #define __SHSUB16 __iar_builtin_SHSUB16
452 #define __USUB16 __iar_builtin_USUB16
453 #define __UQSUB16 __iar_builtin_UQSUB16
454 #define __UHSUB16 __iar_builtin_UHSUB16
455 #define __SASX __iar_builtin_SASX
456 #define __QASX __iar_builtin_QASX
457 #define __SHASX __iar_builtin_SHASX
458 #define __UASX __iar_builtin_UASX
459 #define __UQASX __iar_builtin_UQASX
460 #define __UHASX __iar_builtin_UHASX
461 #define __SSAX __iar_builtin_SSAX
462 #define __QSAX __iar_builtin_QSAX
463 #define __SHSAX __iar_builtin_SHSAX
464 #define __USAX __iar_builtin_USAX
465 #define __UQSAX __iar_builtin_UQSAX
466 #define __UHSAX __iar_builtin_UHSAX
467 #define __USAD8 __iar_builtin_USAD8
468 #define __USADA8 __iar_builtin_USADA8
469 #define __SSAT16 __iar_builtin_SSAT16
470 #define __USAT16 __iar_builtin_USAT16
471 #define __UXTB16 __iar_builtin_UXTB16
472 #define __UXTAB16 __iar_builtin_UXTAB16
473 #define __SXTB16 __iar_builtin_SXTB16
474 #define __SXTAB16 __iar_builtin_SXTAB16
475 #define __SMUAD __iar_builtin_SMUAD
476 #define __SMUADX __iar_builtin_SMUADX
477 #define __SMMLA __iar_builtin_SMMLA
478 #define __SMLAD __iar_builtin_SMLAD
479 #define __SMLADX __iar_builtin_SMLADX
480 #define __SMLALD __iar_builtin_SMLALD
481 #define __SMLALDX __iar_builtin_SMLALDX
482 #define __SMUSD __iar_builtin_SMUSD
483 #define __SMUSDX __iar_builtin_SMUSDX
484 #define __SMLSD __iar_builtin_SMLSD
485 #define __SMLSDX __iar_builtin_SMLSDX
486 #define __SMLSLD __iar_builtin_SMLSLD
487 #define __SMLSLDX __iar_builtin_SMLSLDX
488 #define __SEL __iar_builtin_SEL
489 #define __QADD __iar_builtin_QADD
490 #define __QSUB __iar_builtin_QSUB
491 #define __PKHBT __iar_builtin_PKHBT
492 #define __PKHTB __iar_builtin_PKHTB
499 #define __CLZ __cmsis_iar_clz_not_active
500 #define __SSAT __cmsis_iar_ssat_not_active
501 #define __USAT __cmsis_iar_usat_not_active
502 #define __RBIT __cmsis_iar_rbit_not_active
503 #define __get_APSR __cmsis_iar_get_APSR_not_active
507 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
508 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
509 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
510 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
513 #ifdef __INTRINSICS_INCLUDED
514 #error intrinsics.h is already included previously!
517 #include <intrinsics.h>
527 __STATIC_INLINE uint8_t
__CLZ(uint32_t data)
529 if (data == 0U) {
return 32U; }
532 uint32_t mask = 0x80000000U;
534 while ((data & mask) == 0U)
542 __STATIC_INLINE uint32_t
__RBIT(uint32_t v)
546 for (v >>= 1U; v; v >>= 1U)
558 __asm(
"MRS %0,APSR" :
"=r" (res));
564 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
565 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
568 #define __get_FPSCR() (0)
569 #define __set_FPSCR(VALUE) ((void)VALUE)
572 #pragma diag_suppress=Pe940
573 #pragma diag_suppress=Pe177
575 #define __enable_irq __enable_interrupt
576 #define __disable_irq __disable_interrupt
577 #define __NOP __no_operation
579 #define __get_xPSR __get_PSR
581 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
583 __IAR_FT uint32_t __LDREXW(uint32_t
volatile *ptr)
585 return __LDREX((
unsigned long *)ptr);
588 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t
volatile *ptr)
590 return __STREX(value, (
unsigned long *)ptr);
596 #if (__CORTEX_M >= 0x03)
598 __IAR_FT uint32_t __RRX(uint32_t value)
601 __ASM
volatile(
"RRX %0, %1" :
"=r"(result) :
"r" (value));
605 __IAR_FT
void __set_BASEPRI_MAX(uint32_t value)
607 __asm
volatile(
"MSR BASEPRI_MAX,%0"::
"r" (value));
611 #define __enable_fault_irq __enable_fiq
612 #define __disable_fault_irq __disable_fiq
617 __IAR_FT uint32_t
__ROR(uint32_t op1, uint32_t op2)
619 return (op1 >> op2) | (op1 << ((
sizeof(op1)*8)-op2));
622 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
623 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
625 __IAR_FT uint32_t __get_MSPLIM(
void)
628 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
629 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
633 __asm
volatile(
"MRS %0,MSPLIM" :
"=r" (res));
638 __IAR_FT
void __set_MSPLIM(uint32_t value)
640 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
641 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
645 __asm
volatile(
"MSR MSPLIM,%0" ::
"r" (value));
649 __IAR_FT uint32_t __get_PSPLIM(
void)
652 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
653 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
657 __asm
volatile(
"MRS %0,PSPLIM" :
"=r" (res));
662 __IAR_FT
void __set_PSPLIM(uint32_t value)
664 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
665 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
669 __asm
volatile(
"MSR PSPLIM,%0" ::
"r" (value));
673 __IAR_FT uint32_t __TZ_get_CONTROL_NS(
void)
676 __asm
volatile(
"MRS %0,CONTROL_NS" :
"=r" (res));
680 __IAR_FT
void __TZ_set_CONTROL_NS(uint32_t value)
682 __asm
volatile(
"MSR CONTROL_NS,%0" ::
"r" (value));
685 __IAR_FT uint32_t __TZ_get_PSP_NS(
void)
688 __asm
volatile(
"MRS %0,PSP_NS" :
"=r" (res));
692 __IAR_FT
void __TZ_set_PSP_NS(uint32_t value)
694 __asm
volatile(
"MSR PSP_NS,%0" ::
"r" (value));
697 __IAR_FT uint32_t __TZ_get_MSP_NS(
void)
700 __asm
volatile(
"MRS %0,MSP_NS" :
"=r" (res));
704 __IAR_FT
void __TZ_set_MSP_NS(uint32_t value)
706 __asm
volatile(
"MSR MSP_NS,%0" ::
"r" (value));
709 __IAR_FT uint32_t __TZ_get_SP_NS(
void)
712 __asm
volatile(
"MRS %0,SP_NS" :
"=r" (res));
715 __IAR_FT
void __TZ_set_SP_NS(uint32_t value)
717 __asm
volatile(
"MSR SP_NS,%0" ::
"r" (value));
720 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(
void)
723 __asm
volatile(
"MRS %0,PRIMASK_NS" :
"=r" (res));
727 __IAR_FT
void __TZ_set_PRIMASK_NS(uint32_t value)
729 __asm
volatile(
"MSR PRIMASK_NS,%0" ::
"r" (value));
732 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(
void)
735 __asm
volatile(
"MRS %0,BASEPRI_NS" :
"=r" (res));
739 __IAR_FT
void __TZ_set_BASEPRI_NS(uint32_t value)
741 __asm
volatile(
"MSR BASEPRI_NS,%0" ::
"r" (value));
744 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(
void)
747 __asm
volatile(
"MRS %0,FAULTMASK_NS" :
"=r" (res));
751 __IAR_FT
void __TZ_set_FAULTMASK_NS(uint32_t value)
753 __asm
volatile(
"MSR FAULTMASK_NS,%0" ::
"r" (value));
756 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(
void)
759 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
760 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
764 __asm
volatile(
"MRS %0,PSPLIM_NS" :
"=r" (res));
769 __IAR_FT
void __TZ_set_PSPLIM_NS(uint32_t value)
771 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
772 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
776 __asm
volatile(
"MSR PSPLIM_NS,%0" ::
"r" (value));
780 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(
void)
783 __asm
volatile(
"MRS %0,MSPLIM_NS" :
"=r" (res));
787 __IAR_FT
void __TZ_set_MSPLIM_NS(uint32_t value)
789 __asm
volatile(
"MSR MSPLIM_NS,%0" ::
"r" (value));
796#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
799 __STATIC_INLINE int32_t
__SSAT(int32_t val, uint32_t sat)
801 if ((sat >= 1U) && (sat <= 32U))
803 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
804 const int32_t min = -1 - max ;
817 __STATIC_INLINE uint32_t
__USAT(int32_t val, uint32_t sat)
821 const uint32_t max = ((1U << sat) - 1U);
822 if (val > (int32_t)max)
831 return (uint32_t)val;
835#if (__CORTEX_M >= 0x03)
837 __IAR_FT uint8_t __LDRBT(
volatile uint8_t *addr)
840 __ASM
volatile (
"LDRBT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
841 return ((uint8_t)res);
844 __IAR_FT uint16_t __LDRHT(
volatile uint16_t *addr)
847 __ASM
volatile (
"LDRHT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
848 return ((uint16_t)res);
851 __IAR_FT uint32_t __LDRT(
volatile uint32_t *addr)
854 __ASM
volatile (
"LDRT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
858 __IAR_FT
void __STRBT(uint8_t value,
volatile uint8_t *addr)
860 __ASM
volatile (
"STRBT %1, [%0]" : :
"r" (addr),
"r" ((uint32_t)value) :
"memory");
863 __IAR_FT
void __STRHT(uint16_t value,
volatile uint16_t *addr)
865 __ASM
volatile (
"STRHT %1, [%0]" : :
"r" (addr),
"r" ((uint32_t)value) :
"memory");
868 __IAR_FT
void __STRT(uint32_t value,
volatile uint32_t *addr)
870 __ASM
volatile (
"STRT %1, [%0]" : :
"r" (addr),
"r" (value) :
"memory");
875#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
876 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
879 __IAR_FT uint8_t __LDAB(
volatile uint8_t *ptr)
882 __ASM
volatile (
"LDAB %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
883 return ((uint8_t)res);
886 __IAR_FT uint16_t __LDAH(
volatile uint16_t *ptr)
889 __ASM
volatile (
"LDAH %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
890 return ((uint16_t)res);
893 __IAR_FT uint32_t __LDA(
volatile uint32_t *ptr)
896 __ASM
volatile (
"LDA %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
900 __IAR_FT
void __STLB(uint8_t value,
volatile uint8_t *ptr)
902 __ASM
volatile (
"STLB %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
905 __IAR_FT
void __STLH(uint16_t value,
volatile uint16_t *ptr)
907 __ASM
volatile (
"STLH %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
910 __IAR_FT
void __STL(uint32_t value,
volatile uint32_t *ptr)
912 __ASM
volatile (
"STL %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
915 __IAR_FT uint8_t __LDAEXB(
volatile uint8_t *ptr)
918 __ASM
volatile (
"LDAEXB %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
919 return ((uint8_t)res);
922 __IAR_FT uint16_t __LDAEXH(
volatile uint16_t *ptr)
925 __ASM
volatile (
"LDAEXH %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
926 return ((uint16_t)res);
929 __IAR_FT uint32_t __LDAEX(
volatile uint32_t *ptr)
932 __ASM
volatile (
"LDAEX %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
936 __IAR_FT uint32_t __STLEXB(uint8_t value,
volatile uint8_t *ptr)
939 __ASM
volatile (
"STLEXB %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
943 __IAR_FT uint32_t __STLEXH(uint16_t value,
volatile uint16_t *ptr)
946 __ASM
volatile (
"STLEXH %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
950 __IAR_FT uint32_t __STLEX(uint32_t value,
volatile uint32_t *ptr)
953 __ASM
volatile (
"STLEX %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
960#undef __IAR_M0_FAMILY
963#pragma diag_default=Pe940
964#pragma diag_default=Pe177
966#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
static __inline uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_armcc.h:779
#define __CLZ
Count leading zeros.
Definition: cmsis_armcc.h:558
#define __ROR
Rotate Right in unsigned value (32 bit)
Definition: cmsis_armcc.h:511
#define __RBIT
Reverse bit order of value.
Definition: cmsis_armclang.h:941
static __inline int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_armcc.h:754
#define __REVSH(value)
Reverse byte order (16 bit)
Definition: cmsis_armclang.h:904
static __inline uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_armcc.h:196
Definition: cmsis_iccarm.h:228