RP2040.h File Reference

CMSIS-Core(M) Device Peripheral Access Layer Header File for Device RP2040. More...

#include "core_cm0plus.h"
#include "system_RP2040.h"

Go to the source code of this file.

Macros

#define __CM0PLUS_REV   0x0001U
 
#define __NVIC_PRIO_BITS   2
 
#define __Vendor_SysTickConfig   0
 
#define __VTOR_PRESENT   1
 
#define __MPU_PRESENT   1
 
#define __FPU_PRESENT   0
 
#define __IM   __I
 
#define __OM   __O
 
#define __IOM   __IO
 

Enumerations

enum  IRQn_Type {
  Reset_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 ,
  PendSV_IRQn = -2 , SysTick_IRQn = -1 , TIMER_IRQ_0_IRQn = 0 , TIMER_IRQ_1_IRQn = 1 ,
  TIMER_IRQ_2_IRQn = 2 , TIMER_IRQ_3_IRQn = 3 , PWM_IRQ_WRAP_IRQn = 4 , USBCTRL_IRQ_IRQn = 5 ,
  XIP_IRQ_IRQn = 6 , PIO0_IRQ_0_IRQn = 7 , PIO0_IRQ_1_IRQn = 8 , PIO1_IRQ_0_IRQn = 9 ,
  PIO1_IRQ_1_IRQn = 10 , DMA_IRQ_0_IRQn = 11 , DMA_IRQ_1_IRQn = 12 , IO_IRQ_BANK0_IRQn = 13 ,
  IO_IRQ_QSPI_IRQn = 14 , SIO_IRQ_PROC0_IRQn = 15 , SIO_IRQ_PROC1_IRQn = 16 , CLOCKS_IRQ_IRQn = 17 ,
  SPI0_IRQ_IRQn = 18 , SPI1_IRQ_IRQn = 19 , UART0_IRQ_IRQn = 20 , UART1_IRQ_IRQn = 21 ,
  ADC_IRQ_FIFO_IRQn = 22 , I2C0_IRQ_IRQn = 23 , I2C1_IRQ_IRQn = 24 , RTC_IRQ_IRQn = 25
}
 

Detailed Description

CMSIS-Core(M) Device Peripheral Access Layer Header File for Device RP2040.

Version
V1.0.0
Date
5. May 2021

Macro Definition Documentation

◆ __CM0PLUS_REV

#define __CM0PLUS_REV   0x0001U

CM0PLUS Core Revision

◆ __FPU_PRESENT

#define __FPU_PRESENT   0

FPU present

◆ __IM

#define __IM   __I

< ARM Cortex-M0+ processor and core peripherals

< RP2040 System

< Fallback for older CMSIS versions
Fallback for older CMSIS versions

◆ __MPU_PRESENT

#define __MPU_PRESENT   1

MPU present

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS   2

Number of Bits used for Priority Levels

◆ __OM

#define __OM   __O

Fallback for older CMSIS versions

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

◆ __VTOR_PRESENT

#define __VTOR_PRESENT   1

Set to 1 if CPU supports Vector Table Offset Register

Enumeration Type Documentation

◆ IRQn_Type

enum IRQn_Type
Enumerator
Reset_IRQn 

-15 Reset Vector, invoked on Power up and warm reset

NonMaskableInt_IRQn 

-14 Non maskable Interrupt, cannot be stopped or preempted

HardFault_IRQn 

-13 Hard Fault, all classes of Fault

SVCall_IRQn 

-5 System Service Call via SVC instruction

PendSV_IRQn 

-2 Pendable request for system service

SysTick_IRQn 

-1 System Tick Timer

TIMER_IRQ_0_IRQn 

0 TIMER_IRQ_0

TIMER_IRQ_1_IRQn 

1 TIMER_IRQ_1

TIMER_IRQ_2_IRQn 

2 TIMER_IRQ_2

TIMER_IRQ_3_IRQn 

3 TIMER_IRQ_3

PWM_IRQ_WRAP_IRQn 

4 PWM_IRQ_WRAP

USBCTRL_IRQ_IRQn 

5 USBCTRL_IRQ

XIP_IRQ_IRQn 

6 XIP_IRQ

PIO0_IRQ_0_IRQn 

7 PIO0_IRQ_0

PIO0_IRQ_1_IRQn 

8 PIO0_IRQ_1

PIO1_IRQ_0_IRQn 

9 PIO1_IRQ_0

PIO1_IRQ_1_IRQn 

10 PIO1_IRQ_1

DMA_IRQ_0_IRQn 

11 DMA_IRQ_0

DMA_IRQ_1_IRQn 

12 DMA_IRQ_1

IO_IRQ_BANK0_IRQn 

13 IO_IRQ_BANK0

IO_IRQ_QSPI_IRQn 

14 IO_IRQ_QSPI

SIO_IRQ_PROC0_IRQn 

15 SIO_IRQ_PROC0

SIO_IRQ_PROC1_IRQn 

16 SIO_IRQ_PROC1

CLOCKS_IRQ_IRQn 

17 CLOCKS_IRQ

SPI0_IRQ_IRQn 

18 SPI0_IRQ

SPI1_IRQ_IRQn 

19 SPI1_IRQ

UART0_IRQ_IRQn 

20 UART0_IRQ

UART1_IRQ_IRQn 

21 UART1_IRQ

ADC_IRQ_FIFO_IRQn 

22 ADC_IRQ_FIFO

I2C0_IRQ_IRQn 

23 I2C0_IRQ

I2C1_IRQ_IRQn 

24 I2C1_IRQ

RTC_IRQ_IRQn 

25 RTC_IRQ