CMSIS-Core(M) Device Peripheral Access Layer Header File for Device RP2040. More...
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Macros | |
#define | __CM0PLUS_REV 0x0001U |
#define | __NVIC_PRIO_BITS 2 |
#define | __Vendor_SysTickConfig 0 |
#define | __VTOR_PRESENT 1 |
#define | __MPU_PRESENT 1 |
#define | __FPU_PRESENT 0 |
#define | __IM __I |
#define | __OM __O |
#define | __IOM __IO |
Enumerations | |
enum | IRQn_Type { Reset_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , TIMER_IRQ_0_IRQn = 0 , TIMER_IRQ_1_IRQn = 1 , TIMER_IRQ_2_IRQn = 2 , TIMER_IRQ_3_IRQn = 3 , PWM_IRQ_WRAP_IRQn = 4 , USBCTRL_IRQ_IRQn = 5 , XIP_IRQ_IRQn = 6 , PIO0_IRQ_0_IRQn = 7 , PIO0_IRQ_1_IRQn = 8 , PIO1_IRQ_0_IRQn = 9 , PIO1_IRQ_1_IRQn = 10 , DMA_IRQ_0_IRQn = 11 , DMA_IRQ_1_IRQn = 12 , IO_IRQ_BANK0_IRQn = 13 , IO_IRQ_QSPI_IRQn = 14 , SIO_IRQ_PROC0_IRQn = 15 , SIO_IRQ_PROC1_IRQn = 16 , CLOCKS_IRQ_IRQn = 17 , SPI0_IRQ_IRQn = 18 , SPI1_IRQ_IRQn = 19 , UART0_IRQ_IRQn = 20 , UART1_IRQ_IRQn = 21 , ADC_IRQ_FIFO_IRQn = 22 , I2C0_IRQ_IRQn = 23 , I2C1_IRQ_IRQn = 24 , RTC_IRQ_IRQn = 25 } |
CMSIS-Core(M) Device Peripheral Access Layer Header File for Device RP2040.
#define __CM0PLUS_REV 0x0001U |
CM0PLUS Core Revision
#define __FPU_PRESENT 0 |
FPU present
#define __IM __I |
< ARM Cortex-M0+ processor and core peripherals
< RP2040 System
< Fallback for older CMSIS versions
Fallback for older CMSIS versions
#define __MPU_PRESENT 1 |
MPU present
#define __NVIC_PRIO_BITS 2 |
Number of Bits used for Priority Levels
#define __OM __O |
Fallback for older CMSIS versions
#define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
#define __VTOR_PRESENT 1 |
Set to 1 if CPU supports Vector Table Offset Register
enum IRQn_Type |