27#ifndef __CMSIS_ARMCLANG_H
28#define __CMSIS_ARMCLANG_H
30#pragma clang system_header
33#include <arm_compat.h>
41 #define __INLINE __inline
43#ifndef __STATIC_INLINE
44 #define __STATIC_INLINE static __inline
46#ifndef __STATIC_FORCEINLINE
47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
50 #define __NO_RETURN __attribute__((__noreturn__))
53 #define __USED __attribute__((used))
56 #define __WEAK __attribute__((weak))
59 #define __PACKED __attribute__((packed, aligned(1)))
61#ifndef __PACKED_STRUCT
62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
67#ifndef __UNALIGNED_UINT32
68 #pragma clang diagnostic push
69 #pragma clang diagnostic ignored "-Wpacked"
71 struct __attribute__((packed))
T_UINT32 { uint32_t v; };
72 #pragma clang diagnostic pop
73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
75#ifndef __UNALIGNED_UINT16_WRITE
76 #pragma clang diagnostic push
77 #pragma clang diagnostic ignored "-Wpacked"
80 #pragma clang diagnostic pop
81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
83#ifndef __UNALIGNED_UINT16_READ
84 #pragma clang diagnostic push
85 #pragma clang diagnostic ignored "-Wpacked"
88 #pragma clang diagnostic pop
89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
91#ifndef __UNALIGNED_UINT32_WRITE
92 #pragma clang diagnostic push
93 #pragma clang diagnostic ignored "-Wpacked"
96 #pragma clang diagnostic pop
97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
99#ifndef __UNALIGNED_UINT32_READ
100 #pragma clang diagnostic push
101 #pragma clang diagnostic ignored "-Wpacked"
104 #pragma clang diagnostic pop
105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
108 #define __ALIGNED(x) __attribute__((aligned(x)))
111 #define __RESTRICT __restrict
113#ifndef __COMPILER_BARRIER
114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
119#ifndef __PROGRAM_START
120#define __PROGRAM_START __main
124#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
128#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
131#ifndef __VECTOR_TABLE
132#define __VECTOR_TABLE __Vectors
135#ifndef __VECTOR_TABLE_ATTRIBUTE
136#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
170 __ASM
volatile (
"MRS %0, control" :
"=r" (result) );
175#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
181__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(
void)
185 __ASM
volatile (
"MRS %0, control_ns" :
"=r" (result) );
198 __ASM
volatile (
"MSR control, %0" : :
"r" (control) :
"memory");
202#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
208__STATIC_FORCEINLINE
void __TZ_set_CONTROL_NS(uint32_t control)
210 __ASM
volatile (
"MSR control_ns, %0" : :
"r" (control) :
"memory");
224 __ASM
volatile (
"MRS %0, ipsr" :
"=r" (result) );
238 __ASM
volatile (
"MRS %0, apsr" :
"=r" (result) );
252 __ASM
volatile (
"MRS %0, xpsr" :
"=r" (result) );
266 __ASM
volatile (
"MRS %0, psp" :
"=r" (result) );
271#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
277__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(
void)
281 __ASM
volatile (
"MRS %0, psp_ns" :
"=r" (result) );
292__STATIC_FORCEINLINE
void __set_PSP(uint32_t topOfProcStack)
294 __ASM
volatile (
"MSR psp, %0" : :
"r" (topOfProcStack) : );
298#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
304__STATIC_FORCEINLINE
void __TZ_set_PSP_NS(uint32_t topOfProcStack)
306 __ASM
volatile (
"MSR psp_ns, %0" : :
"r" (topOfProcStack) : );
320 __ASM
volatile (
"MRS %0, msp" :
"=r" (result) );
325#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
331__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(
void)
335 __ASM
volatile (
"MRS %0, msp_ns" :
"=r" (result) );
346__STATIC_FORCEINLINE
void __set_MSP(uint32_t topOfMainStack)
348 __ASM
volatile (
"MSR msp, %0" : :
"r" (topOfMainStack) : );
352#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
358__STATIC_FORCEINLINE
void __TZ_set_MSP_NS(uint32_t topOfMainStack)
360 __ASM
volatile (
"MSR msp_ns, %0" : :
"r" (topOfMainStack) : );
365#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
371__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(
void)
375 __ASM
volatile (
"MRS %0, sp_ns" :
"=r" (result) );
385__STATIC_FORCEINLINE
void __TZ_set_SP_NS(uint32_t topOfStack)
387 __ASM
volatile (
"MSR sp_ns, %0" : :
"r" (topOfStack) : );
401 __ASM
volatile (
"MRS %0, primask" :
"=r" (result) );
406#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
412__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(
void)
416 __ASM
volatile (
"MRS %0, primask_ns" :
"=r" (result) );
429 __ASM
volatile (
"MSR primask, %0" : :
"r" (priMask) :
"memory");
433#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
439__STATIC_FORCEINLINE
void __TZ_set_PRIMASK_NS(uint32_t priMask)
441 __ASM
volatile (
"MSR primask_ns, %0" : :
"r" (priMask) :
"memory");
446#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
447 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
448 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
449 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
455#define __enable_fault_irq __enable_fiq
463#define __disable_fault_irq __disable_fiq
471__STATIC_FORCEINLINE uint32_t __get_BASEPRI(
void)
475 __ASM
volatile (
"MRS %0, basepri" :
"=r" (result) );
480#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
486__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(
void)
490 __ASM
volatile (
"MRS %0, basepri_ns" :
"=r" (result) );
501__STATIC_FORCEINLINE
void __set_BASEPRI(uint32_t basePri)
503 __ASM
volatile (
"MSR basepri, %0" : :
"r" (basePri) :
"memory");
507#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
513__STATIC_FORCEINLINE
void __TZ_set_BASEPRI_NS(uint32_t basePri)
515 __ASM
volatile (
"MSR basepri_ns, %0" : :
"r" (basePri) :
"memory");
526__STATIC_FORCEINLINE
void __set_BASEPRI_MAX(uint32_t basePri)
528 __ASM
volatile (
"MSR basepri_max, %0" : :
"r" (basePri) :
"memory");
537__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(
void)
541 __ASM
volatile (
"MRS %0, faultmask" :
"=r" (result) );
546#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
552__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(
void)
556 __ASM
volatile (
"MRS %0, faultmask_ns" :
"=r" (result) );
567__STATIC_FORCEINLINE
void __set_FAULTMASK(uint32_t faultMask)
569 __ASM
volatile (
"MSR faultmask, %0" : :
"r" (faultMask) :
"memory");
573#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
579__STATIC_FORCEINLINE
void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
581 __ASM
volatile (
"MSR faultmask_ns, %0" : :
"r" (faultMask) :
"memory");
591#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
592 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
593 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
604__STATIC_FORCEINLINE uint32_t __get_PSPLIM(
void)
606#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
607 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
608 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
613 __ASM
volatile (
"MRS %0, psplim" :
"=r" (result) );
618#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
628__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(
void)
630#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
631 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
636 __ASM
volatile (
"MRS %0, psplim_ns" :
"=r" (result) );
652__STATIC_FORCEINLINE
void __set_PSPLIM(uint32_t ProcStackPtrLimit)
654#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
655 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
656 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
658 (void)ProcStackPtrLimit;
660 __ASM
volatile (
"MSR psplim, %0" : :
"r" (ProcStackPtrLimit));
665#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
675__STATIC_FORCEINLINE
void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
677#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
678 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
680 (void)ProcStackPtrLimit;
682 __ASM
volatile (
"MSR psplim_ns, %0\n" : :
"r" (ProcStackPtrLimit));
696__STATIC_FORCEINLINE uint32_t __get_MSPLIM(
void)
698#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
699 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
700 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
705 __ASM
volatile (
"MRS %0, msplim" :
"=r" (result) );
711#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
720__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(
void)
722#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
723 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
728 __ASM
volatile (
"MRS %0, msplim_ns" :
"=r" (result) );
743__STATIC_FORCEINLINE
void __set_MSPLIM(uint32_t MainStackPtrLimit)
745#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
746 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
747 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
749 (void)MainStackPtrLimit;
751 __ASM
volatile (
"MSR msplim, %0" : :
"r" (MainStackPtrLimit));
756#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
765__STATIC_FORCEINLINE
void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
767#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
768 (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
770 (void)MainStackPtrLimit;
772 __ASM
volatile (
"MSR msplim_ns, %0" : :
"r" (MainStackPtrLimit));
786#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
787 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
788#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
790#define __get_FPSCR() ((uint32_t)0U)
798#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
799 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
800#define __set_FPSCR __builtin_arm_set_fpscr
802#define __set_FPSCR(x) ((void)(x))
818#if defined (__thumb__) && !defined (__thumb2__)
819#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
820#define __CMSIS_GCC_RW_REG(r) "+l" (r)
821#define __CMSIS_GCC_USE_REG(r) "l" (r)
823#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
824#define __CMSIS_GCC_RW_REG(r) "+r" (r)
825#define __CMSIS_GCC_USE_REG(r) "r" (r)
832#define __NOP __builtin_arm_nop
838#define __WFI __builtin_arm_wfi
846#define __WFE __builtin_arm_wfe
853#define __SEV __builtin_arm_sev
862#define __ISB() __builtin_arm_isb(0xF)
869#define __DSB() __builtin_arm_dsb(0xF)
877#define __DMB() __builtin_arm_dmb(0xF)
886#define __REV(value) __builtin_bswap32(value)
895#define __REV16(value) __ROR(__REV(value), 16)
904#define __REVSH(value) (int16_t)__builtin_bswap16(value)
914__STATIC_FORCEINLINE uint32_t
__ROR(uint32_t op1, uint32_t op2)
921 return (op1 >> op2) | (op1 << (32U - op2));
932#define __BKPT(value) __ASM volatile ("bkpt "#value)
941#define __RBIT __builtin_arm_rbit
949__STATIC_FORCEINLINE uint8_t
__CLZ(uint32_t value)
964 return __builtin_clz(value);
968#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
969 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
970 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
971 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
972 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
980#define __LDREXB (uint8_t)__builtin_arm_ldrex
989#define __LDREXH (uint16_t)__builtin_arm_ldrex
998#define __LDREXW (uint32_t)__builtin_arm_ldrex
1009#define __STREXB (uint32_t)__builtin_arm_strex
1020#define __STREXH (uint32_t)__builtin_arm_strex
1031#define __STREXW (uint32_t)__builtin_arm_strex
1038#define __CLREX __builtin_arm_clrex
1047#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1048 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1049 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1050 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1059#define __SSAT __builtin_arm_ssat
1069#define __USAT __builtin_arm_usat
1079__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
1083 __ASM
volatile (
"rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1094__STATIC_FORCEINLINE uint8_t __LDRBT(
volatile uint8_t *ptr)
1098 __ASM
volatile (
"ldrbt %0, %1" :
"=r" (result) :
"Q" (*ptr) );
1099 return ((uint8_t) result);
1109__STATIC_FORCEINLINE uint16_t __LDRHT(
volatile uint16_t *ptr)
1113 __ASM
volatile (
"ldrht %0, %1" :
"=r" (result) :
"Q" (*ptr) );
1114 return ((uint16_t) result);
1124__STATIC_FORCEINLINE uint32_t __LDRT(
volatile uint32_t *ptr)
1128 __ASM
volatile (
"ldrt %0, %1" :
"=r" (result) :
"Q" (*ptr) );
1139__STATIC_FORCEINLINE
void __STRBT(uint8_t value,
volatile uint8_t *ptr)
1141 __ASM
volatile (
"strbt %1, %0" :
"=Q" (*ptr) :
"r" ((uint32_t)value) );
1151__STATIC_FORCEINLINE
void __STRHT(uint16_t value,
volatile uint16_t *ptr)
1153 __ASM
volatile (
"strht %1, %0" :
"=Q" (*ptr) :
"r" ((uint32_t)value) );
1163__STATIC_FORCEINLINE
void __STRT(uint32_t value,
volatile uint32_t *ptr)
1165 __ASM
volatile (
"strt %1, %0" :
"=Q" (*ptr) :
"r" (value) );
1180__STATIC_FORCEINLINE int32_t
__SSAT(int32_t val, uint32_t sat)
1182 if ((sat >= 1U) && (sat <= 32U))
1184 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1185 const int32_t min = -1 - max ;
1205__STATIC_FORCEINLINE uint32_t
__USAT(int32_t val, uint32_t sat)
1209 const uint32_t max = ((1U << sat) - 1U);
1210 if (val > (int32_t)max)
1219 return (uint32_t)val;
1228#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1229 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
1230 (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1238__STATIC_FORCEINLINE uint8_t __LDAB(
volatile uint8_t *ptr)
1242 __ASM
volatile (
"ldab %0, %1" :
"=r" (result) :
"Q" (*ptr) :
"memory" );
1243 return ((uint8_t) result);
1253__STATIC_FORCEINLINE uint16_t __LDAH(
volatile uint16_t *ptr)
1257 __ASM
volatile (
"ldah %0, %1" :
"=r" (result) :
"Q" (*ptr) :
"memory" );
1258 return ((uint16_t) result);
1268__STATIC_FORCEINLINE uint32_t __LDA(
volatile uint32_t *ptr)
1272 __ASM
volatile (
"lda %0, %1" :
"=r" (result) :
"Q" (*ptr) :
"memory" );
1283__STATIC_FORCEINLINE
void __STLB(uint8_t value,
volatile uint8_t *ptr)
1285 __ASM
volatile (
"stlb %1, %0" :
"=Q" (*ptr) :
"r" ((uint32_t)value) :
"memory" );
1295__STATIC_FORCEINLINE
void __STLH(uint16_t value,
volatile uint16_t *ptr)
1297 __ASM
volatile (
"stlh %1, %0" :
"=Q" (*ptr) :
"r" ((uint32_t)value) :
"memory" );
1307__STATIC_FORCEINLINE
void __STL(uint32_t value,
volatile uint32_t *ptr)
1309 __ASM
volatile (
"stl %1, %0" :
"=Q" (*ptr) :
"r" ((uint32_t)value) :
"memory" );
1319#define __LDAEXB (uint8_t)__builtin_arm_ldaex
1328#define __LDAEXH (uint16_t)__builtin_arm_ldaex
1337#define __LDAEX (uint32_t)__builtin_arm_ldaex
1348#define __STLEXB (uint32_t)__builtin_arm_stlex
1359#define __STLEXH (uint32_t)__builtin_arm_stlex
1370#define __STLEX (uint32_t)__builtin_arm_stlex
1385#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1387#define __SADD8 __builtin_arm_sadd8
1388#define __QADD8 __builtin_arm_qadd8
1389#define __SHADD8 __builtin_arm_shadd8
1390#define __UADD8 __builtin_arm_uadd8
1391#define __UQADD8 __builtin_arm_uqadd8
1392#define __UHADD8 __builtin_arm_uhadd8
1393#define __SSUB8 __builtin_arm_ssub8
1394#define __QSUB8 __builtin_arm_qsub8
1395#define __SHSUB8 __builtin_arm_shsub8
1396#define __USUB8 __builtin_arm_usub8
1397#define __UQSUB8 __builtin_arm_uqsub8
1398#define __UHSUB8 __builtin_arm_uhsub8
1399#define __SADD16 __builtin_arm_sadd16
1400#define __QADD16 __builtin_arm_qadd16
1401#define __SHADD16 __builtin_arm_shadd16
1402#define __UADD16 __builtin_arm_uadd16
1403#define __UQADD16 __builtin_arm_uqadd16
1404#define __UHADD16 __builtin_arm_uhadd16
1405#define __SSUB16 __builtin_arm_ssub16
1406#define __QSUB16 __builtin_arm_qsub16
1407#define __SHSUB16 __builtin_arm_shsub16
1408#define __USUB16 __builtin_arm_usub16
1409#define __UQSUB16 __builtin_arm_uqsub16
1410#define __UHSUB16 __builtin_arm_uhsub16
1411#define __SASX __builtin_arm_sasx
1412#define __QASX __builtin_arm_qasx
1413#define __SHASX __builtin_arm_shasx
1414#define __UASX __builtin_arm_uasx
1415#define __UQASX __builtin_arm_uqasx
1416#define __UHASX __builtin_arm_uhasx
1417#define __SSAX __builtin_arm_ssax
1418#define __QSAX __builtin_arm_qsax
1419#define __SHSAX __builtin_arm_shsax
1420#define __USAX __builtin_arm_usax
1421#define __UQSAX __builtin_arm_uqsax
1422#define __UHSAX __builtin_arm_uhsax
1423#define __USAD8 __builtin_arm_usad8
1424#define __USADA8 __builtin_arm_usada8
1425#define __SSAT16 __builtin_arm_ssat16
1426#define __USAT16 __builtin_arm_usat16
1427#define __UXTB16 __builtin_arm_uxtb16
1428#define __UXTAB16 __builtin_arm_uxtab16
1429#define __SXTB16 __builtin_arm_sxtb16
1430#define __SXTAB16 __builtin_arm_sxtab16
1431#define __SMUAD __builtin_arm_smuad
1432#define __SMUADX __builtin_arm_smuadx
1433#define __SMLAD __builtin_arm_smlad
1434#define __SMLADX __builtin_arm_smladx
1435#define __SMLALD __builtin_arm_smlald
1436#define __SMLALDX __builtin_arm_smlaldx
1437#define __SMUSD __builtin_arm_smusd
1438#define __SMUSDX __builtin_arm_smusdx
1439#define __SMLSD __builtin_arm_smlsd
1440#define __SMLSDX __builtin_arm_smlsdx
1441#define __SMLSLD __builtin_arm_smlsld
1442#define __SMLSLDX __builtin_arm_smlsldx
1443#define __SEL __builtin_arm_sel
1444#define __QADD __builtin_arm_qadd
1445#define __QSUB __builtin_arm_qsub
1447#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1448 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1450#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1451 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1453#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1455__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1459 __ASM
volatile (
"smmla %0, %1, %2, %3" :
"=r" (result):
"r" (op1),
"r" (op2),
"r" (op3) );
static __inline uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: cmsis_armclang.h:248
static __inline uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: cmsis_armclang.h:262
static __inline void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: cmsis_armclang.h:196
static __inline uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: cmsis_armclang.h:316
static __inline uint32_t __get_CONTROL(void)
Enable IRQ Interrupts.
Definition: cmsis_armclang.h:166
static __inline uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition: cmsis_armclang.h:1205
static __inline void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: cmsis_armclang.h:346
static __inline uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: cmsis_armclang.h:397
static __inline uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: cmsis_armclang.h:220
static __inline uint32_t __get_APSR(void)
Get APSR Register.
Definition: cmsis_armclang.h:234
static __inline void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: cmsis_armclang.h:427
static __inline void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: cmsis_armclang.h:292
static __inline int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition: cmsis_armclang.h:1180
static __inline uint8_t __CLZ(uint32_t value)
Count leading zeros.
Definition: cmsis_armclang.h:949
static __inline uint32_t __ROR(uint32_t op1, uint32_t op2)
Rotate Right in unsigned value (32 bit)
Definition: cmsis_armclang.h:914
Definition: cmsis_armclang.h:87
Definition: cmsis_armclang.h:79
Definition: cmsis_armclang.h:103
Definition: cmsis_armclang.h:95
Definition: cmsis_armclang.h:71