verilator

Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling. More information: https://veripool.org/guide/latest/.

verilator --binary --build-jobs 0 -Wall path/to/source.v

verilator --cc --exe --build --build-jobs 0 -Wall path/to/source.cpp path/to/output.v

verilator --lint-only -Wall

verilator --xml-output -Wall path/to/output.xml